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參數(shù)資料
| 型號： | T8534 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號處理器 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 890K |
| 代理商： | T8534 |
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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
22
Agere Systems Inc.
Functional Description
(continued)
The Control Interface
(continued)
Fast Scan Mode
(continued)
0124e
* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait
≥
1.5
μ
s after the second full DCLK cycle
and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and
DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final
DCLK cycles are required to process the read data.
Two or more DCLK cycles are required before the start of a new command frame.
Figure 17. Fast Scan, Byte-by-Byte Mode (Continuous DCLK)
0126f
Note: CK1 through CK8 are additional DCLK pulses required to properly process the data.
Figure 18. Fast Scan, Byte-by-Byte Mode (Gapped DCLK)
1
2
3
CS
DCLK
DI
COMMAND
DATA
4
5
DO
WAIT
≥
1.5
μ
s
0
1
2
3
4
5
6
7
6
7
0
1
2
3
4
5
6
7
0
*
1
2
3
CS
DCLK
DI
COMMAND
DATA
4
5
DO
WAIT
≥
1.5
μ
s
0
1
2
3
4
5
6
7
6
7
0
1
2
3
4
5
6
7
0
C
C
C
C
C
C
C
C
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