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參數(shù)資料
| 型號(hào)： | T8534 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號(hào)處理器 |
| 文件頁數(shù)： | 25/48頁 |
| 文件大小： | 890K |
| 代理商： | T8534 |
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Agere Systems Inc.
25
Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
Functional Description
(continued)
Echo Canceller Functionality
The echo canceller has three sets of coefficient mem-
ory storage locations. One, called HPRE, contains the
default balance coefficients and can be accessed as
memory addresses 0—127. This serves as the coeffi-
cients for a fixed balance network (adaptation dis-
abled), or as a starting point for echo cancelllation. The
contents of these memory locations do not change with
adaptation. The adaptation coefficients, which are
added to the corresponding coefficients in HPRE, are
stored in the HHAT area. Normally, the user has no
need to access these coefficients; thus, these
addresses are not described in this data sheet. The
HHAT coefficients cover either the first 8, 16, 32, or the
entire 64-tap length of the balance filter, depending on
the settings in the LMSGAIN address. Note that all
echo canceller length options in this control location
may not be implemented, but are reserved for future
use.
A third set of coefficients is contained in HDTA, which
are used for special data call functions.
SLIC Control Capabilities
Memory locations 158, 159, and 160 are used to con-
trol six bidirectional latches that are intended to allow
the serial interface to control other line card devices,
such as ringing/test switches, telecom electromechani-
cal relays, and SLIC devices. When the TTL latches
are configured as outputs, external devices should be
set up to sink current from the latch. Location 158 sets
the operational mode of these latches as either inputs
or outputs. Location 159 specifies what is to be written
on the latch leads driven by the device. Location 160
reports the actual state of these leads. It should be
noted that a channel control reset forces all of these
external leads, except those corresponding to bits 2
and 3, to the high-impedance state, so any inputs con-
nected to bits 0, 1, 4, and 5 should have appropriate
pull-up or pull-down resistors (off-chip, if required) to
force the external device into a known state at power-
up or in the event of a reset. Bits 2 and 3 will reset to
outputs with a value of zero.
The fast scan mode allows for a minimal data transfer
on the serial bus to monitor bits 0 and 1 of the SLIC
data memory location (159). If these 2 bits are wired as
inputs to the off-hook and/or ring ground detection cir-
cuits, a convenient method of rapidly scanning for
these two functions is obtained. Bits 2 and 3 default to
outputs; thus, they are convenient to provide control of
the SLIC state. In any event, all six leads are program-
mable for maximum flexibility.
Suggested Initialization Procedures
It is suggested that upon powerup, a hardware reset be
used to set the device into a known state. The serial
interface should then be used to load the memory
addresses that differ from the default values (the write
all channels command is convenient for this function).
If other devices are controlled by the SLIC data mem-
ory location, then it also should be loaded with a known
configuration. After the completion of this sequence,
the device is ready to be activated. Depending on the
application, the next step may either be normal opera-
tion or a set of test sequences. After the initialization of
the memory, the device and associated line card
devices can be controlled by using memory locations
130, 131, 145, 155, 156, 157, 158, 159, and 129; that
is, by supplying the PCM bus time-slot addresses,
switching the SLIC into the proper mode, and activating
the codec. Within memory location 129, the codec
would normally be placed into active mode, with both
directions of the PCM bus enabled at the start of a call.
At the completion of a call, the codec should be placed
into standby mode and the PCM bus disabled. Great
caution should be used when changing the memory
while the codec is in active mode, since termination
impedances, balance impedances, and gains may
change. These changes are likely to yield undesirable
system effects. It is safe to refresh coefficients that are
known to be unchanging in the application. It is always
possible to read the memory to verify its contents with-
out deleterious effects on codec operation. Normal
operation would load the memory and perform all gain
adjustments while the codec is in standby mode. Under
no circumstances should memory above address 162
be written, since this section of memory is used for
state data and intermediate results. Also, all reserved
addresses should not be written. Changing this infor-
mation may have deleterious effects on system opera-
tion.
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