參數(shù)資料
型號(hào)： TMS320VC5409PGE-80
廠商： Texas Instruments
文件頁數(shù)： 14/93頁
文件大?。?/td> 0K
描述： IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C54x
類型： 定點(diǎn)
接口： 主機(jī)接口，McBSP
時(shí)鐘速率： 80MHz
非易失內(nèi)存： ROM（32 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
配用： 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
21
April 1999 Revised October 2008
SPRS082F
3
Functional Overview
The following functional overview is based on the block diagram in Figure 31.
GPIO
MBus
32K RAM
Dual Access
Program/Data
McBSP1
McBSP2
McBSP3
RHEA Bus
APLL
TIMER
JTAG
Clocks
RHEAbus
RHEA
Bridge
TI BUS
xDMA
logic
16K Program
ROM
Pbus
Cbus
Dbus
Ebus
RHEA
bus
MBus
Pbus
Cbus
Dbus
Ebus
Pbus
Enhanced XIO
P, C, D, E Buses and Control Signals
XIO
HPI
54X cLEAD
HPI
Figure 31. TMS320VC5409 Functional Block Diagram
3.1
CPU Core
The TMS320VC5409 is based on the TMS320C54x (cLEAD v2) DSP core, and is completely code compatible
with other 54x products. The core includes the following features:
LEAD2 CPU
Software programmable wait-state generator with bank-switching wait-state logic
External memory interface
Program space
Data space
I/O space
Scan-based emulation logic
3.1.1 Software Programmable WaitState Generator
The software wait-state generator of the 5409 is similar to that of the 5410 and it can extend external bus cycles
by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using
the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks
to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the
power consumption of the 5409.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the system configuration register (SCR) defines
a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to
provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 32
and described in Table 31.
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