參數(shù)資料
型號(hào)： TMS320VC5409PGE-80
廠商： Texas Instruments
文件頁(yè)數(shù)： 17/93頁(yè)
文件大?。?/td> 0K
描述： IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C54x
類型： 定點(diǎn)
接口： 主機(jī)接口，McBSP
時(shí)鐘速率： 80MHz
非易失內(nèi)存： ROM（32 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
配用： 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
24
April 1999 Revised October 2008
SPRS082F
Table 33. Bank-Switching Control Register Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
RESET
VALUE
FUNCTION
1512
BNKCMP
1111
Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four
MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 1215) are compared, resulting
in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
11
PS-DS
1
Program read data read access. PS-DS inserts an extra cycle between consecutive accesses of program
read and data read or data read and program read.
PS-DS = 0
No extra cycles are inserted by this feature.
PS-DS = 1
One extra cycle is inserted between consecutive data and program reads.
103
Reserved
0
These bits are reserved and are unaffected by writes.
HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset
.
8-bit Mode
HBH = 0
The bus holder is disabled for the HPI data bus (HD[7:0]).
HBH = 1
The bus holders are enabled on HD[7:0]. When not driven, the HPI data bus (HD[7:0]) is held
in the previous logic level.
2
HBH
0
HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset
.
16-bit Mode
HBH = 0
The bus holder is disabled for the HPI address bus (HA[15:0]). The HPI GPIO pins (HD[7:0])
are held in the previous logic level.
HBH = 1
The bus holders are enabled on HA[15:0]. When not driven, the HPI address bus (A[15:0])
and HPI GPIO pins (HD[7:0]) are held in the previous logic level.
1
BH
0
Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
The bus holder is disabled.
BH = 1
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the previous
logic level.
0
EXIO
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
The external bus interface functions as usual.
EXIO = 1
The address bus, data bus, and control signals become inactive after completing the current
bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1
cannot be modified when the interface is disabled.
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