參數(shù)資料
型號(hào): TMS320VC5409PGE-80
廠商: Texas Instruments
文件頁(yè)數(shù): 50/93頁(yè)
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
54
April 1999 Revised October 2008
SPRS082F
5.6
Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in the
clock generator section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table. Table 54 and Table 55 assumes testing over recommended operating
conditions and H = 0.5tc(CO) (see Figure 54).
Table 54.
Multiply-By-N Clock Option (PLL Enabled) Timing Requirements
MIN
MAX
UNIT
Integer PLL multiplier N (N = 115)
20
200
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.5
20
100
ns
tc(CI)
Cycle time, X2/CLKIN
PLL multiplier N = x.25, x.75
20
50
ns
tf(CI)
Fall time, X2/CLKIN
8
ns
tr(CI)
Rise time, X2/CLKIN
8
ns
tw(CIL)
Pulse duration, X2/CLKIN low
5
ns
tw(CIH)
Pulse duration, X2/CLKIN high
5
ns
N = Multiplication factor
The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
Table 55.
Multiply-By-N Clock Option (PLL Enabled) Switching Characteristics
PARAMETER
80
100
UNIT
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
tc(CO)
Cycle time, CLKOUT
12.5
tc(CI)/N
10
tc(CI)/N
ns
td(CI-CO)
Delay time, X2/CLKIN high/low to CLKOUT high/low
4
10
17
4
10
17
ns
tf(CO)
Fall time, CLKOUT
2
ns
tr(CO)
Rise time, CLKOUT
2
ns
tw(COL)
Pulse duration, CLKOUT low
H3
H1
H
H2
H1
H
ns
tw(COH)
Pulse duration, CLKOUT high
H3
H1
H
H2
H1
H
ns
tp
Transitory phase, PLL lock up time
30
ms
N = Multiplication factor
tc(CO)
tc(CI)
tw(COH)
tf(CO)
tr(CO)
tf(CI)
X2/CLKIN
CLKOUT
td(CI-CO)
tw(COL)
tr(CI)
tp
Unstable
tw(CIH)
tw(CIL)
Figure 54. External Multiply-by-One Clock Timing
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