Table 532. HPI8 Mode Switching Characteristics
參數(shù)資料
型號(hào): TMS320VC5409PGE-80
廠商: Texas Instruments
文件頁(yè)數(shù): 77/93頁(yè)
文件大小: 0K
描述: IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
79
April 1999 Revised October 2008
SPRS082F
Table 532. HPI8 Mode Switching Characteristics§
PARAMETER
MIN
MAX
UNIT
ten(DSL-HD)
Enable time, HD driven from DS low
2
19
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) < 18H
18H+19 – tw(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
tw(DSH) ≥ 18H
19
td(DSL-HDV1)
Delay time, DS low to HDx valid for
first byte of an HPI read
Case 1c: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) < 26H
26H+19 – tw(DSH)
ns
td(DSL-HDV1)
Delay time, DS low to HDx valid for
first byte of an HPI read
Case 1d: Memory access when
DMAC is active in 32-bit mode and
tw(DSH) ≥ 26H
19
ns
Case 2a: Memory accesses when
DMAC is inactive and tw(DSH) < 10H
10H+19 – tw(DSH)
Case 2b: Memory accesses when
DMAC is inactive and tw(DSH) ≥ 10H
19
Case 3: Register accesses
19
td(DSL-HDV2)
Delay time, DS low to HDx valid for second byte of an HPI read
19
ns
th(DSH-HDV)R
Hold time, HDx valid after DS high, for a HPI read
3
5
ns
tv(HYH-HDV)
Valid time, HDx valid after HRDY high
5
td(DSH-HYL)
Delay time, DS high to HRDY low (see Note 1)
10
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
18H+10
ns
td(DSH-HYH)
Delay time, DS high to HRDY high
Case 1b: Memory accesses when
DMAC is active in 32-bit mode
26H+10
ns
td(DSH-HYH)
Delay time, DS high to HRDY high
Case 2: Memory accesses when
DMAC is inactive
10H+10
ns
Case 3: Write accesses to HPIC
register (see Note 2)
6H+10
ns
td(HCS-HRDY)
Delay time, HCS low/high to HRDY low/high
15
ns
td(COH-HYH)
Delay time, CLKOUT high to HRDY high
2
ns
td(COH-HTX)
Delay time, CLKOUT high to HINT change
5
ns
NOTES:
1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
DS refers to the logical OR of HCS, HDS1, and HDS2.
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
§ DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
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