Transmit and Receive Switc" />
參數(shù)資料
型號: TMS320VC5409PGE-80
廠商: Texas Instruments
文件頁數(shù): 69/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C54x
類型: 定點
接口: 主機接口,McBSP
時鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
71
April 1999 Revised October 2008
SPRS082F
Table 520. McBSP
Transmit and Receive Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tc(BCKRX)
Cycle time, BCLKR/X
BCLKR/X int
4H
ns
tw(BCKRXH)
Pulse duration, BCLKR/X high
BCLKR/X int
D3
D+1
ns
tw(BCKRXL)
Pulse duration, BCLKR/X low
BCLKR/X int
C3
C+1
ns
td(BCKRH-BFRV)
Delay time, BCLKR high to internal BFSR valid
BCLKR int
2
ns
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
BCLKX int
0
6
ns
td(BCKXH-BFXV)
Delay time, BCLKX high to internal BFSX valid
BCLKX ext
4
12
ns
tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit
BCLKX int
4
7
ns
tdis(BCKXH-BDXHZ) Disable time, BCLKX high to BDX high impedance following last data bit
BCLKX ext
3
9
ns
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
BCLKX int
0
7
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
bit transmitted.
BCLKX ext
4
12
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 1
DXENA = 0
BCLKX int
7
ns
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
DXENA = 0
BCLKX ext
12
te(BCKXH-BDX)
Enable time, BCLKX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 1
DXENA = 0
BCLKX int
4
ns
te(BCKXH-BDX)
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
DXENA = 0
BCLKX ext
2
ns
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 0
DXENA = 0
BFSX int
2
ns
td(BFXH-BDXV)
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
DXENA = 0
BFSX ext
12
ns
te(BFXH-BDX)
Enable time, BFSX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 0
DXENA = 0
BFSX int
1
ns
te(BFXH-BDX)
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
DXENA = 0
BFSX ext
2
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
T=BCLKRX period = (1 + CLKGDV) * 2H
C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable
(DXENA) and data delay features of the McBSP.
The transmit delay enable (DXENA) and A-bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5409.
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