Table 516 assumes te" />
參數(shù)資料
型號(hào): TMS320VC5409PGE-80
廠商: Texas Instruments
文件頁(yè)數(shù): 63/93頁(yè)
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
66
April 1999 Revised October 2008
SPRS082F
5.10 Reset, BIO, Interrupt, and MP/MC Timings
Table 516 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 514,
Figure 515, and Figure 516).
Table 516. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
MAX
UNIT
th(RS)
Hold time, RS after CLKOUT low
0
ns
th(BIO)
Hold time, BIO after CLKOUT low
0
ns
th(INT)
Hold time, INTn, NMI, after CLKOUT low
0
ns
th(MPMC)
Hold time, MP/MC after CLKOUT low
0
ns
tw(RSL)
Pulse duration, RS low§
4H+4
ns
tw(BIO)S
Pulse duration, BIO low, synchronous
2H+1
ns
tw(BIO)A
Pulse duration, BIO low, asynchronous
4H
ns
tw(INTH)S
Pulse duration, INTn, NMI high (synchronous)
2H+1
ns
tw(INTH)A
Pulse duration, INTn, NMI high (asynchronous)
4H
ns
tw(INTL)S
Pulse duration, INTn, NMI low (synchronous)
2H+1
ns
tw(INTL)A
Pulse duration, INTn, NMI low (asynchronous)
4H
ns
tw(INTL)WKP
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
8
ns
tsu(RS)
Setup time, RS before X2/CLKIN low
6
ns
tsu(BIO)
Setup time, BIO before CLKOUT low
7
10
ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
8
10
ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
8
ns
The external interrupts (INT0INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 s to ensure synchronization
and lock-in of the PLL.
§ Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
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