Table 529. McBSP as SPI Master or Slave Timing Requirements (CLKST" />
參數(shù)資料
型號: TMS320VC5409PGE-80
廠商: Texas Instruments
文件頁數(shù): 75/93頁
文件大小: 0K
描述: IC FIXED POINT DSP 144-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C54x
類型: 定點
接口: 主機接口,McBSP
時鐘速率: 80MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Documentation Support
77
April 1999 Revised October 2008
SPRS082F
Table 529. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
UNIT
tsu(BDRV-BCKXL)
Setup time, BDR valid before BCLKX low
10
12H
ns
th(BCKXL-BDRV)
Hold time, BDR valid after BCLKX low
0
5 + 12H
ns
tsu(BFXL-BCKXL)
Setup time, BFSX low before BCLKX low
10
ns
tc(BCKX)
Cycle time, BCLKX
32H
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 530. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
PARAMETER
MASTER
SLAVE
UNIT
PARAMETER
MIN
MAX
MIN
MAX
UNIT
th(BCKXH-BFXL)
Hold time, BFSX low after BCLKX high§
D 4
D + 4
ns
td(BFXL-BCKXL)
Delay time, BFSX low to BCLKX low
T 5
T + 3
ns
td(BCKXH-BDXV)
Delay time, BCLKX high to BDX valid
3
7
6H + 5
10H + 14
ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
2
4
6H + 3
10H + 17
ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
C 1
C + 4
4H 2
8H + 17
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C =
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D =
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
BCLKX
BFSX
BDX
BDR
td(BFXL-BCKXL)
tsu(BDRV-BCKXL)
tdis(BCKXH-BDXHZ)
th(BCKXH-BFXL)
td(BCKXH-BDXV)
th(BCKXL-BDRV)
td(BFXL-BDXV)
LSB
MSB
tsu(BFXL-BCKXL)
tc(BCKX)
Figure 526. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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