SPRS457E
– MARCH 2009 – REVISED JUNE 2011
– RESET must be low until all supplies are ramped up.
– Steps 1, 2, and 3 may be performed simultaneously if the Main core finishes ramping up before the
I/Os and the maximum delta voltage difference between the 1.8-V and 3.3-V I/Os is 2.0-V until the
1.8-V I/O reaches the full voltage.
The following steps should be followed for the restricted power-off method:
1. Power off Main/Analog I/O (3.3-V).
2. Power off PRTCSS/Main I/O (1.8-V).
3. Power off PRTCSS/Main core (1.2-V or 1.35-V).
Notes for restricted power-off:
– The 3.3-/1.8-V I/Os may be powered off simultaneously if the maximum delta voltage difference
between them is 2.0V until the 1.8-V I/O is completely powered off, and the PRTCSS/Main core
must be powered down last.
When booting the DM365 from OneNAND, you must ensure that the OneNAND device is ready with valid
program instructions before the DM365 attempts to read program instructions from it. In particular, before
you release the device's reset, you must allow time for OneNAND device power to stabilize and for the
OneNAND device to complete its internal copy routine. During the internal copy routine, the OneNAND
device copies boot code from its internal non-volatile memory to its internal boot memory section. Board
designers typically achieve this requirement by design of the system power and reset supervisor circuit.
Refer to your OneNAND device datasheet for OneNAND power ramp and stabilization times and for
OneNAND boot copy times.
6.4.3
Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the device to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the device, the PC board should include separate power planes for core, I/O, and ground, all
bypassed with high-quality low-ESL/ESR capacitors.
6.4.4
Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the device. These caps need to be close to the power pins, no more than 1.25 cm
maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560
pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a
small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per
supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the
corners of the "exterior".
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 uF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of
any component, verification of capacitor availability over the product
’s production lifetime should be
considered. See also
Section 6.6.1 for additional recommendations on power supplies for the
oscillator/PLL supplies.
Copyright
2009–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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