SPRS457E
– MARCH 2009 – REVISED JUNE 2011
Table 6-56. Universal Serial Bus (USB) Registers (continued)
Offset
Acronym
Register Description
414h
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
416h
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint.
(Index register set to select Endpoints 1-4)
HOST_RXCSR
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
418h
COUNT0
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
41Ah
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for
the host Transmit endpoint.
(Index register set to select Endpoints 1-4)
41Bh
HOST_NAKLIMIT0
Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host Transmit endpoint. (Index register set to
select Endpoints 1-4)
41Ch
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for
the host Receive endpoint.
(Index register set to select Endpoints 1-4)
41Dh
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
timeout on Bulk transactions for host Receive endpoint. (Index register set to select
Endpoints 1-4)
41Fh
CONFIGDATA
Returns details of core configuration. (Index register set to select Endpoint 0)
FIFOn
420h
FIFO0
Transmit and Receive FIFO Register for Endpoint 0
424h
FIFO1
Transmit and Receive FIFO Register for Endpoint 1
428h
FIFO2
Transmit and Receive FIFO Register for Endpoint 2
42Ch
FIFO3
Transmit and Receive FIFO Register for Endpoint 3
430h
FIFO4
Transmit and Receive FIFO Register for Endpoint 4
OTG Device Control
460h
DEVCTL
OTG Device Control Register
Dynamic FIFO Control
462h
TXFIFOSZ
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4)
463h
RXFIFOSZ
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4)
464h
TXFIFOADDR
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4)
466h
RXFIFOADDR
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4)
Target Endpoint 0 Control Registers, Valid Only in Host Mode
480h
TXFUNCADDR
Address of the target function that has to be accessed through the associated
Transmit Endpoint.
482h
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit
Endpoint. This is used only when full speed or low speed device is connected via a
USB2.0 high-speed hub.
483h
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint.
This is used only when full speed or low speed device is connected via a USB2.0
high-speed hub.
484h
RXFUNCADDR
Address of the target function that has to be accessed through the associated
Receive Endpoint.
152
Peripheral Information and Electrical Specifications
Copyright
2009–2011, Texas Instruments Incorporated