參數(shù)資料
型號(hào): TMX320DM365AZCE
廠商: Texas Instruments
文件頁(yè)數(shù): 35/210頁(yè)
文件大小: 0K
描述: IC DIGITAL MEDIA SOC 338-NFBGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320DM3x, DaVinci™
類型: 數(shù)字媒體片內(nèi)系統(tǒng)(DMSoC)
接口: HPI,I²C,McBSP,MMC,SD,SPI,UART,USB
時(shí)鐘速率: 300MHz
非易失內(nèi)存: ROM(16 kB)
芯片上RAM: 32kB
電壓 - 輸入/輸出: 1.8V,3.3V
電壓 - 核心: 1.35V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 338-LFBGA
供應(yīng)商設(shè)備封裝: 338-NFBGA(13x13)
包裝: 托盤(pán)
其它名稱: 296-24397
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SPRS457E
– MARCH 2009 – REVISED JUNE 2011
2.5
Power Management
The device is designed for minimal power consumption. There are two components to power
consumption: active power and leakage power. Active power is the power consumed to perform work and
scales with clock frequency and the amount of computations being performed. Active power can be
reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to
complete the required operation in the required time-line or to run at a clock setting until the work is
complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be
performed. Leakage power is due to static current leakage and occurs regardless of the clock rate.
Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating
junction temperatures. Leakage power can only be avoided by removing power completely from a device
or subsystem. The device includes several power management modes which are briefly described in
Table 2-2. See the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number
SPRUFG5) for more information on power management.
Table 2-2. Power Management Conditions
GIO,
SPI,
POWER MGMT.
OTHER
DDR
CORE
OSC.
PLL
ARM926
UART,
PWM,
APPLICATION
PRTCSS
PERIPH.
CLOCK/
DESCRIPTION
POWER
CNTRLR.
CLOCK
I2C
TIMER
SCENARIO
CLOCKS
MODE
CLOCKS
This condition
consumes the lowest
PRTCSS
Active
Off
possible power, except
for the PRTCSS.
This mode consumes
the second lowest
Bypass
Suspend /
possible power, except
Mode
Deep Sleep Mode(1)
Active
On
Off
"Self-
for PRTCSS and core
(not
Refresh"
power, where only the
Active)
deep sleep circuit is on
in this mode.
This condition keeps
the minimum possible
modules powered-on
Suspend /
in order to wake up the
Bypass
Standby
Active
On
Off
On
Off
"Self-
device. Clocks are
Mode
Refresh"
suspended except for
GIO (interrupts),
UART, and I2C (in
slave mode).
Most clocks are
suspended, except for
ARM, GIO, UART,
SPI, I2C, PWM, and
Suspend /
Low-power
Bypass
timers. Since ARM will
Active
On
On / Off
"Self-
(PLL Bypass Mode)
Mode
not have access to
Refresh"
DDR, its internal
Cache will be either
frozen or not
accessed.
The device, including
Nominal
system PLLs, are on.
System Running
Active
On
PLL Mode
On
On / Off
Clock /
This condition
(PLL Mode)
Operation
conserves the least
amount of power.
(1)
For more details, see TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5)
Copyright
2009–2011, Texas Instruments Incorporated
Device Overview
13
Product Folder Link(s): TMS320DM365
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