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| 型號： | TPS650732TRSLRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 0.4 MM PITCH, GREEN, PLASTIC, QFN-48 |
| 文件頁數(shù)： | 27/90頁 |
| 文件大小： | 1375K |
| 代理商： | TPS650732TRSLRQ1 |
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/RESET
THRESHOLD
Vbat
delay
Vref=1V
+
-
RESET
Vbat
THRESHOLD
T RESET
comparator
output(internal)
www.ti.com
SLVSAP7 – JANUARY 2011
Optionally, there is internal sequencing for the DCDC converters and both LDOs available. Bits DCDC_SQ[0..2]
in register CON_CTRL1 define the start-up and shut-down sequence for the DCDC converters. Depending on
the sequencing option, the signal at EN_DCDC1, EN_DCDC2 and EN_DCDC3 are ignored. For automatic
internal sequencing, the enable signals which are not used should be connected to GND.
LDO1 and LDO2 will start up automatically as defined in register LDO_CTRL1. See details about the sequencing
options in the register description for CON_CTRL1 and LDO_CTRL1.
RESET
The contain circuitry that can generate a reset pulse for a processor with a certain delay time. The input voltage
at a comparator is sensed at an input called THRESHOLD. When the voltage exceeds the threshold, the output
goes high with the delay time defined in register PGOOD. The reset circuitry is not active in OFF-state. The
pull-up resistor for this open drain output must not be connected directly to the battery as this may cause a
leakage path when the power path (SYS voltage) is turned off. The reset delay time equals the setting for the
PGOOD signal.
Figure 32. Reset Timing
PGOOD (reset signal for applications processor)
This open drain output generates a power-good signal depending on the status of the power good Bits for the
DCDC converters and the LDOs. Register PGOODMASK defines which of the power good Bits of the converters
and LDOs are used to drive the external PGOOD signal low when the voltage is below the target value. If e.g.,
Bit MASK DCDC2 is set to 1, the PGOOD pin will be driven low as long as the output of DCDC2 is below the
target voltage. If the output voltage of DCDC2 rises to its nominal value, the PGOOD pin will be released after
the delay time defined. See the default settings in the register description.
PB_IN (Push-button IN)
This pin is the ON/OFF button for the PMU to leave OFF-state and enter ON-state by pulling this pin to GND.
Entering ON-state will first ramp the output voltage of the power path (SYS), load the default register settings and
start up the DCDC converters and LDOs with the sequencing defined. In ON-state, the I2C interface is active and
the wLED converter can be enabled. The system turns on if PB_IN is pulled LOW for >50ms (debounce time)
AND the output voltage of the power path manager is above the undervoltage lockout voltage (AVDD6 > 3V).
This is for Vbat>3V OR VAC>3V OR VUSB>3V. The default voltage for the undervoltage lockout voltage can be
changed with Bits <UVLO1>, <UVLO0> in register CON_CTRL2. The value will be valid until the device was
turned off completely by entering Off state. The system turns off if PB_IN is released OR the system voltage falls
below the undervoltage lockout voltage of 3V. This is the case when either the battery voltage drops below 3.0V
or the input voltage at the pins AC or USB is below 3V. In order to keep the enabled after PB_IN is released
HIGH, there is an input pin called POWER_ON which needs to be pulled HIGH before the PB_IN button is
released. POWER_ON=HIGH will typically be asserted by the application processor to keep the PMU in
ON-state after the power button at PB_IN is released.
Copyright 2011, Texas Instruments Incorporated
33
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