參數(shù)資料
型號(hào)： TPS650732TRSLRQ1
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 0.4 MM PITCH, GREEN, PLASTIC, QFN-48
文件頁(yè)數(shù)： 68/90頁(yè)
文件大?。?/td> 1375K
代理商： TPS650732TRSLRQ1
SLVSAP7 – JANUARY 2011
www.ti.com
POWER SOLUTIONS FOR DIFFERENT APPLICATION PROCESSORS
Default Settings
For proper power supply design with , not only the default output voltage is relevant but also in what sequence
the different power rails are enabled. The voltages are typically enabled internally based on the sequencing
options programmed. For different application processors, there are different sequencing options available. In
addition, the delay time and pulse for the reset signal to the application processor is different. See Table 9 with
the default settings for sequencing, output voltages and reset options for the family:
Table 9. Sequencing Settings
DEDICATED
DCDC_SQ[2..0]
LDO_SQ[2..0]
COMMENT
FOR
Starting
was developed for battery powered applications with focus on lowest shutdown and quiescent current. In order to
achieve this, in shutdown all mayor blocks and the system voltage at the output of the power path (SYS) are
turned off and only the input that turns on , pin PB_IN, is supervised. is designed such that only an ON-key on
PB_IN is needed pulling this pin LOW to enable . No external pull-up is needed as this is integrated into .
Once PB_IN is pulled LOW, the system voltage is ramped and the dcdc converters and LDOs are started with
the sequencing defined for the version used. If PB_IN is released again, TPS6507x would turn off, so a pin was
introduced to keep TPS6507x enabled after PB_IN was released. Pin POWER_ON serves this function and
needs to be pulled HIGH before the user releases the ON-key (PB_IN = HIGH). This HIGH signal at
POWER_ON can be provided by the GPIO of a processor or by a pull-up resistor to any voltage in the system
which is higher than 1.2V. Pulling POWER-ON to a supply voltage would significantly reduce the time PB_IN has
to be asserted LOW. If POWER_ON is tied to a GPIO, the processor has to boot up first which may take some
time. In this case however, the processor could do some additional debouncing, hence does not keep the power
enabled if the ON-key is only pressed for a short time. When there is a supply voltage for the battery charger at
pins AC or USB, the situation is slightly different. In this case, the power path is enabled and the system voltage
(SYS) has ramped already to whatever the voltage at AC or USB is. The dcdc converters are not enabled yet but
the start-up could not only be done by pulling PB_IN=LOW but also by pulling POWER_ON=HIGH.
In applications that do not require an ON-key but shall power-up automatically once supply voltage is applied,
there are two cases to consider. If TPS6507x is powered from its AC or USB pin (not powered from its BAT pin),
POWER-ON just needs to be pulled HIGH to enable the converters. PB_IN must not be tied LOW in this case.
If TPS6507x is powered from its BAT pin, PB_IN needs to be tied LOW to start-up the converters.
Layout Considerations
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues as
well as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short traces
for the main current paths. The input capacitors should be placed as close as possible to the IC pins as well as
the inductor and output capacitor.
For TPS6507x, connect the PGND pin of the device to the PowerPAD land of the PCB and connect the analog
ground connection (GND) to the PGND at the PowerPAD. The PowerPAD serves as the power ground
connection for the DCDC1 and DCDC2 converters. Therefore it is essential to provide a good thermal and
electrical connection to GND using multiple vias to the GND-plane. Keep the common path to the GND pin,
which returns the small signal components, and the high current of the output capacitors as short as possible to
avoid ground noise. The VDCDCx line should be connected right to the output capacitor and routed away from
noisy components and traces (for example, the L1, L2, L3 and L4 traces). See the EVM users guide for details
about the layout for TPS6507x.
70
Copyright 2011, Texas Instruments Incorporated
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