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參數(shù)資料
| 型號： | TS83102G0BMGS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152 |
| 文件頁數(shù)： | 29/54頁 |
| 文件大?。?/td> | 2622K |
| 代理商： | TS83102G0BMGS |
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35
0935B–BDC–06/08
e2v semiconductors SAS 2008
TS83102G0BMGS
9.
TS83102G0BMGS Operating Features
9.1
Timing Information
9.1.1
Timing Value for TS83102G0BMGS
The timing values are defined in the “Electrical Operating Characteristics” on page 4.
The timing values are given at the package inputs/outputs, taking into account the package’s transmis-
sion line, bond wire, pad and ESD protections capacitance, as well as specified termination loads. The
evaluation board propagation delays in 50
Ω controlled impedance traces are not taken into account. You
should apply proper derating values corresponding to termination topology.
9.1.2
Propagation Time Considerations
The TOD and TDR timing values are given from the package pin to pin and do not include the additional
propagation times between the device pins and input/output termination loads. For the evaluation board,
the propagation time delay is 6.1 ps/mm (155 ps/inch) corresponding to a 3.4 dielectric constant (at 10
GHz) of the RO4003 used for the board.
If a different dielectric layer is used (for instance Teflon), you should use appropriate propagation time
values.
TD1 and TD2 do not depend on propagation times because they are differential data (see “Definition of
TD1 and TD2 are also the most straightforward data to measure, because they are differential: TD can
be measured directly on the termination loads, with matching oscilloscope probes.
9.1.3
TOD-TDR Variation Over Temperature
Values for TOD and TDR track each other over the temperature (there is a 1% variation for TOD and
TDR per 100
°C temperature variation). Therefore the TOD and TDR variation over temperature is negli-
gible. Moreover, the internal (on-chip) skews between each TOD and TDR data effect can be considered
negligible. Consequently, the minimum values for TOD and TDR are never more than 100 ps apart. The
same is true for their maximum values.
However, the external TOD and TDR values can be dictated by the total digital data skews between
each TOD and TDR. These digital skews can include the MCM board, bonding wires and output line
length differences, as well as output termination impedance mismatches.
The external (on-board) skew effect has not been taken into account for the specification of TOD and
TDR minimum and maximum values.
9.1.4
Principle of Operation
The analog input is sampled on the rising edge of the external clock’s input (CLK/CLKB) after TA (aper-
ture delay). The digitized data is available after 4 clock periods’ latency (pipeline delay [TPD]) on the
clock’s rising edge, after a typical propagation delay TOD. The Data Ready differential output signal fre-
quency (DR/DRB) is half the external clock’s frequency. It switches at the same rate as the digital
outputs. The Data Ready output signal (DR/DRB) switches on the external clock’s falling edge after a
propagation delay TDR.
If TOD equals TDR, the rising edge (True-False) of the differential Data Ready signal is placed in the
middle of the Output Data Valid window. This gives maximum setup and hold times for external data
acquisition.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0BVGL | 制造商:e2v technologies 功能描述:ADC SGL 2GSPS 10-BIT PARALLEL 152CBGA - Trays |
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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