參數(shù)資料
型號(hào)： TS83102G0BMGS
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝： 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152
文件頁數(shù)： 31/54頁
文件大?。?/td> 2622K
代理商： TS83102G0BMGS
37
0935B–BDC–06/08
e2v semiconductors SAS 2008
TS83102G0BMGS
9.2.3
Timing Diagram
Figure 9-1.
TS83102G0BMGS Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at LOW Level
Figure 9-2.
TS83102G0BMGS Timing Diagram (2 Gsps Clock Rate) - Data Ready Reset Clock Held at HIGH Level
9.3
Analog Inputs (VIN/VINB)
9.3.1
Static Issues: Differential vs. Single-ended (Full-scale Inputs)
The ADC’s front-end Track and Hold differential preamplifier has been designed to be entered either in
differential or single-ended mode, up to the maximum operating speed of 2.2 Gsps, without affecting
dynamic performances (it does not require a single to differential balun).
In a single-ended input configuration, the in-phase full-scale input amplitude is 0.5V peak-to-peak, cen-
tered on 0V (or –2 dBm into 50
Ω).
N - 4
N - 3
N - 2
N - 1
N
N + 1
VIN/VINB
CLK/CLKB
Digital
Outputs
Data Ready
DR/DRB
Data Ready
Reset
TA = 160 ps
N
N + 1
N + 2
N + 3
N - 5
TOD = 360 ps
TDR = 410 ps
TRDR = 1000 ps
1 ns
TC = 500 ps
TC1 TC2
TPD = 4.0 Clock Period
TOD = 360 ps
500 ps
TDR = 410 ps
TD1 = TC1 + TDR - TOD
= TC1 + 50 ps = 300 ps
TD2 = TC2 + TOD - TDR
= TC2 - 50 ps = 200 ps
N - 4
N - 3
N - 2
N - 1
N
N + 1
N - 5
500 ps
TD2 = TC2 + TOD - TDR
= TC2 - 50 ps = 200 ps
TD1 = TC1 + TDR - TOD
= TC1 + 50 ps = 300 ps
TDR = 410 ps
TPD = 4.0 Clock Periods
TOD = 360 ps
TRDR = 1000 ps
1 ns
TDR = 410 ps
TOD = 360 ps
TA = 160 ps
N
N + 1
N + 2
N + 3
TC = 500 ps
TC1
TC2
VIN/VINB
CLK/CLKB
Digital
Outputs
Data Ready
DR/DRB
Data Ready
Reset
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