參數(shù)資料
型號(hào): TS83102G0BMGS
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152
文件頁(yè)數(shù): 51/54頁(yè)
文件大?。?/td> 2622K
代理商: TS83102G0BMGS
6
0935B–BDC–06/08
TS83102G0BMGS
e2v semiconductors SAS 2008
Note:
1. Differential output buffers impedance = 100
Ω differential (50Ω single-ended). See.Figure 9-7 on page 41
2. Histogram testing at Fs = 1 Gsps, Fin = 100 MHz, DNLrms is a component of quantization noise.
3. Histogram testing at Fs = 50 Msps, Fin = 25 MHz.
4. This range of gain can be set to 1 by using the gain adjust function.
Logic compatibility (depending on VPLUSD value)
LVDS (VPLUSD = 1.4 V typical)
Output levels 50
Ω transmission lines, 100Ω
(2 x 50
Ω) differentially terminated
- logic low
- logic high
- swing (each single-ended output)
- common mode
max. VPLUSD = 1.525V
typ. V
PLUSD = 1.45V
min. VPLUSD = 1.375V
4
V
OL
VOH
VOH - VOL
825
200
1190
1125
1090
1310
230
1200
1575
300
1275
1210
mV
DC Accuracy
DNLrms (2)
4
DNLrms
0.50
0.53
0.55
LSB
Differential nonlinearity (3)
1
DNL+
1.5
2
LSB
Integral nonlinearity (3)
1
INL-
–4.0
–2.4
LSB
Integral nonlinearity (3)
1INL+
2.4
4.0
LSB
Gain central value (4)
1
0.89
0.94
1.1
Gain error drift
4
23
35
ppm/
°C
Input offset voltage
1
–10
10
mV
Table 3-3.
Electrical Operating Characteristics (Continued)
V
CC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode
voltage and performances are guaranteed within the limits of the specified V
PLUSD range (from 0.9V to 1.7V);
V
EE = DVEE = 5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven. (Continued)
Parameter
Test
Level
Symbol
Min
Typ
Max
Unit
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