參數(shù)資料
型號: TS83102G0BMGS
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, HERMETIC SEALED, CERAMIC, CGA-152
文件頁數(shù): 42/54頁
文件大?。?/td> 2622K
代理商: TS83102G0BMGS
47
0935B–BDC–06/08
e2v semiconductors SAS 2008
TS83102G0BMGS
9.7.8
ADC Gain Control
The ADC gain is adjustable by using pin R9 of the CI-CGA package. The gain adjust transfer function is
Figure 9-16. Gain Adjust Transfer Function
9.7.9
Sampling Delay Adjust
The sampling delay adjust (SDA pin) enables you to fine-tune the sampling ADC aperture delay TAD
around its nominal value (160 ps). This functionality is enabled with the SDAEN signal, which is active
when tied to V
EE and inactive when tied to GND.
This feature is particularly interesting for interleaving ADCs to increase the sampling rate.
The variation of the delay around its nominal value as a function of the SDA voltage is shown in Figure 9-
17 (simulation result).
Figure 9-17. Typical Tuning Range (±120 ps for Applied Control Voltage Varying Between 0.5V and 0.5V on
the SDA Pin)
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
VGA Gain Adjust Voltage (V)
ADC
G
a
in
Min
Typical
400 p
300 p
200 p
100 p
-500 m
-400 m
-300 m
-200 m
-100 m
0.00
100 m
200 m
300 m
400 m
500
Delay in the Variable Delay Cell at 60C
SDA Voltage
Delay(s)
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