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| 型號： | TVP3010-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(110MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標(biāo)，伽瑪校正貴賓（110MHz的，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 12/100頁 |
| 文件大小： | 571K |
| 代理商： | TVP3010-110 |
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1–6
1.5
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
44, 54, 56, 80
Ground. All GND terminals must be connected. The GNDs are
connected internally.
HSYNCOUT
46
O
(TTL
compatible)
Horizontal sync output after pipeline delay. For system mode the
output can be programmed, but for the VGA mode the output
carries the same polarity as the input.
Analog current outputs. These outputs can drive a 37.5-
load
directly (doubly terminated 75-
line), thus eliminating the
requirement for any external buffering.
IOR, IOG, IOB
48, 49, 50
O
MUXOUT [SENSE]
63
O
(TTL
compatible)
Multiplexer output control or DAC comparator output signal.
When this terminal is configured as a multiplexer output control,
it is software programmable through the configuration register.
When the multiplexer control register is set to VGA mode, this
output terminal and corresponding configuration register bit are
set low to indicate to external devices that VGA pass through
mode is being used. Alternatively, this terminal can be configured
as the DAC comparator output. In this case, the terminal is low
if one or more of the DAC output analog levels is above the
internal comparator reference of 350 mV
50 mV.
P(0–31)
1–29, 82–84
I
(TTL
compatible)
Pixel input port. The port can be used in various modes as shown
in the multiplexer control register. All the unused terminals need
to be tied to GND.
REF
53
Voltage reference for DACs. An internal voltage reference of
nominally 1.235 V is provided, which requires an external 0.1-
μ
F
ceramic capacitor between REF and analog GND. However, the
internal reference voltage can be overdriven by an externally
supplied reference voltage. Typical connection is shown in
Appendix A.
Read strobe input. A logic 0 on this terminal initiates a read from
the register map. Reads are performed asynchronously and are
initiated on the low-going edge of RD (see Figure 3–1).
RD
31
I
(TTL
compatible)
RS(0–2)
32–34
I
(TTL
compatible)
Register-select inputs. These terminals specify the location in the
register map that is to be accessed (see Table 2–1).
RS3, [PSEL]
35
I
(TTL
compatible)
Register-select input or port-select input. When configured as the
RS3 input, this terminal has no effect. When configured as the
port select input, this terminal allows the creation of VGA or
overlay windows in a direct color background on a pixel-by-pixel
basis.
SCLK
79
O
(TTL
compatible)
Shift-clock output. SCLK is selected as a division of the dot clock
input. The output signals are gated off during blank, although
SCLK is still used internally to synchronize with the activation of
blank.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
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