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| 型號： | TVP3010-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(110MHz,高/寬光標，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標，伽瑪校正貴賓（110MHz的，高/寬光標，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 22/100頁 |
| 文件大小： | 571K |
| 代理商： | TVP3010-110 |
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low until the sampled SYSBL signal goes back high. At this time, SCLK is enabled to clock the first pixel data
valid from VRAM. The TVP3010 video blanking circuitry is designed with sufficient pipeline delay to allow
the internal sampled SYSBL and VGABL signals to align with the pipelined RGB data to the video DACs.
The logic described above works in situations where the SCLK period is shorter than, equal to, or longer
than the VCLK period.
When in the self-clocked mode, the SCLK control timing is designed to interface directly with the external
VRAM. The shift register in the system VRAM is supposed to be updated during the blank active period.
When the SYSBL input is sampled high by the falling edge of VCLK, the VRAM shift clock (SCLK) is restarted
to clock the VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the
TVP3010 pixel input port. The second SCLK causes the VRAM shift register to shift out the second group
of data. At the same time, LCLK latches the first group of pixel data into the VIP (refer to Figure 2–2 for a
detailed timing diagram).
The RCLK/SCLK phase relationship is designed such that timing specifications are satisfied for the case
where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is
required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the
signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK
period –7 ns. Please refer to the timing parameter specifications for more details.
When the VRAM split shift-register operation is performed (see Figure 2–3), the SCLK timing is adjusted
to work with the SFLAG input. Basically, the split shift-register operation inserts an SCLK during the blank
period. This causes the first group of pixel data to appear at the pixel port during blank and allows the first
group of data to be displayed as soon as the palette comes out of blank. Figures 2–3 and 2–5 show the case
when the SSRT (split shift-register transfer) function is enabled. When a rising edge occurs on the SFLAG
input, one SCLK with a minimum 15-ns pulse duration is generated after the specified delay. Since this is
designed to meet VRAM timing requirements, the SSRT-generated SCLK replaces the first SCLK in the
regular shift register transfer case as described above. Refer to Section 2.15 for a detailed explanation of
the SSRT function.
Externally clocked timing can be chosen for the pixel bus [P(0–31)] by setting auxiliary control register bit 3
to a logic 0. In externally clocked mode, the RCLK or SCLK output of the palette is not used as the timing
reference to present data to the pixel bus. Instead, pixel data is presented to the palette with a synchronous
clock and all palette timing is referenced to this clock. In this mode, the external clock should be connected
to LCLK and the selected clock input. (If the VGA port is enabled, the CLK0 input is selected independent
of the input clock selection register.)
The externally clocked frame-buffer interface mode is intended for applications where windowed or
pixel-by-pixel switching between the VGA port and the pixel port is desired in non-VRAM-based graphics
systems. In such applications, the VGA port is enabled (multiplex-control register bit 7 set to logic 1) and
the appropriate direct-color mode is set in the multiplex-control register. The auxiliary window, port select,
and/or color-key switching functions are then configured and enabled to perform the desired switching. By
setting the frame-buffer interface to the externally clocked mode, the pixel port and VGA port timing and
pipeline delay are made the same. Also, since the VGA port is enabled, all video control signal timing is
referenced to CLK0, utilizing the VGABL, HSYNC, and VSYNC inputs.
The externally clocked frame-buffer interface timing can also be used in non-VGA switching applications,
utilizing only the pixel port or only the VGA port. In either case, it is recommended that VGA video-control
signals be used (i.e., VGABL, HSYNC, VSYNC). In this way, all pixel data and video control signals are
referenced to CLK0 and video blank and sync are aligned with pixel data.
NOTE:
If the pixel port is used in externally clocked mode (ACR3 = 0), RCLK must be set
to DOT/1 in the output-clock-selection register and a 1:1 multiplexing mode must
be selected in the multiplexer control registers (see Table 2–6). The external clock
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| TVP3010-135 | Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標，伽馬校正，視頻接口調(diào)色板) |
| TVP3010-170 | Hardware Cursor, GAMMA Correction VIP(170MHz,高/寬光標，伽馬校正，視頻接口調(diào)色板) |
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| TVP3010C | Video Interface Palette |
| TVP3010M | Video Interface Palette |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010-110FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-135MGA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-135MGAB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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