參數(shù)資料
型號(hào)： TVP3010-110
廠商： Texas Instruments, Inc.
英文描述： Hardware Cursor, GAMMA Correction VIP(110MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
中文描述： 硬件光標(biāo)，伽瑪校正貴賓（110MHz的，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板）
文件頁(yè)數(shù)： 26/100頁(yè)
文件大?。?/td> 571K
代理商： TVP3010-110
2–12
always provides the first pixel to be displayed in the pseudo-color or true-color multiplexing modes. The
difference between little- and big-endian data formats and how they affect the pixel bus operation is
discussed in detail in Appendix C.
2.4.2
The VGA pass-through mode is used to emulate the VGA modes of most personal computers. The
advantage of this mode is that it can take data presented on the feature connector of most VGA-compatible
PC systems into the device on a separate bus, thus requiring no external multiplexing. This feature is
particularly useful in systems where the existing graphics circuitry is on the motherboard. In this instance,
it enables a drop-in graphics card to be implemented that maintains compatibility with all existing software.
This is accomplished by using the on-board VGA circuitry but routing the emerging bit-plane data through
the TVP3010 palette. VGA pass-through is the default mode at power up or reset.
VGA Pass-Through Mode
Since this mode is designed with the feature connector philosophy, all data latching and control timing is
referenced to CLK0. When the VGA port is enabled (MCR2 bit 7 = 1), CLK0 is selected as the input clock
source independent of the input-clock-selection register. The VGA port always operates as in the externally
clocked mode of the pixel port [P(0–31)]; it receives the VGA data [VGA(0–7)] and the VGA blank (VGABL),
both of which are referenced to an external clock (CLK0). CLK0 also latches the VGABL, HSYNC, and
VSYNC video-control signals when in the VGA pass-through mode. External signals on LCLK have no effect
on the VGA port since LCLK only latches data on the pixel port [P(0–31)].
VGA data pipeline delay is adjusted within the TVP3010 palette depending on whether self- or externally-
clocked frame-buffer interface timing is used (see Section 2.3.2). If TVP3010 is programmed for self-clocked
timing, additional dot clock pipeline delay is inserted into the internal VGA data path. The purpose is so that
the VGA and pixel port data can remain synchronous when doing auxiliary window, port select, or
color-keyed switching (see Section 2.6). The additional VGA pipeline delay accounts for the dot clock to
RCLK pipeline delay within the palette.
2.4.3
In pseudo-color mode (sometimes called color indexing), the pixel-bus inputs are used to address the
palette-RAM LUT (color lookup table). The data in each RAM location is comprised of 24 bits (8 bits for each
of the red, green, and blue color DACs). The pseudo-color mode is further grouped into 4 submodes,
depending on the data bits per pixel. In each submode, a pixel bus width of 4, 8, 16, or 32 bits may be used.
Data should always be presented on the least significant bits of the pixel bus; i.e., when 16 bits are used,
the pixel data must be presented on P(15–0), 8 bits on P(7–0), and 4 bits on P(3–0). See Tables 2–6
through 2–11 for more details.
Pseudo-Color Mode
Submode 1 uses a single bit plane to address the color palette. The pixel port bit is fed into bit 0 of the palette
address, with the 7 high-order address bits defined by the palette-page register (see Section 2.2.3). This
mode has uses in high-resolution monochrome applications such as desktop publishing. This mode allows
the maximum amount of multiplexing with 32:1 ratio, thus giving a pixel bus rate of only 4 MHz at a screen
resolution of 1280-by-1024. Although only a single bit is used, alteration of the palette-page register at the
line frequency allows 256 different colors to be displayed per screen with two colors per line.
Submode 2 uses two bit planes to address the color palette. The two bits are fed into the low-order address
bits of the palette with the six high-order address bits being defined by the palette-page register (see
Section 2.2.3). This mode allows a maximum multiplex ratio of 16:1 on the pixel bus and is essentially a
four-color alternative to submode 1.
Submode 3 uses four bit planes to address the color palette. The four bits are fed into the low-order address
bits of the palette with the four high-order address bits being defined by the palette-page register (see
Section 2.2.3). This mode provides 16 pages of 16 colors and can be used at multiplex ratios of /1 to /8.
Submode 4 uses eight bit planes to address the color palette. Since all eight bits of palette address are
specified from the pixel port, the page register is not used. This mode allows dot clock-to-LCLK ratios of 1:1
相關(guān)PDF資料
PDF描述
TVP3010-135 Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
TVP3010-170 Hardware Cursor, GAMMA Correction VIP(170MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
TVP3010-85 Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
TVP3010C Video Interface Palette
TVP3010M Video Interface Palette
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3010-110FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3010-135FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3010-135MGA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3010-135MGAB 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3010-170FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
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