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參數(shù)資料
| 型號： | TVP3010-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(110MHz,高/寬光標，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標，伽瑪校正貴賓（110MHz的，高/寬光標，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 21/100頁 |
| 文件大?。?/td> | 571K |
| 代理商： | TVP3010-110 |
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2–7
The output-clock-selection register is used to program the desired divided-down frequencies for the
reference/shift and video clocks.
Table 2–5. Output-Clock-Selection Register Format
OUTPUT-CLOCK-SELECTION-REGISTER BITS (see Note 4)
6
5
4
3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
FUNCTION (see Notes 4 5 6 and 7)
FUNCTION (see Notes 4, 5, 6, and 7)
2
x
x
x
x
x
x
1
x
x
x
x
x
x
0
x
x
x
x
x
x
VCLK/1 output ratio
VCLK/2 output ratio
VCLK/4 output ration
VCLK/8 output ratio
VCLK/16 output ratio
VCLK/32 output ratio
1
1
0
x
x
x
VCLK/64 output ratio
VCLK output held at logic 1
1
1
1
x
x
x
x
x
x
0
0
0
RCLK/1 output ratio (see Notes 4 and 7)
x
x
x
0
0
1
RCLK/2 output ratio (see Notes 4 and 7)
x
x
x
0
1
0
RCLK/4 output ratio (see Notes 4 and 7)
x
x
x
0
1
1
RCLK/8 output ratio (see Notes 4 and 7)
x
x
x
1
0
0
RCLK/16 output ratio (see Notes 4 and 7)
x
x
x
1
0
1
RCLK/32 output ratio (see Notes 4 and 7)
x
x
x
1
1
0
RCLK/64 output ratio (see Notes 4 and 7)
RCLK/64, SCLK output held at logic 0
0
x
x
x
1
1
0
0
x
x
x
1
1
1
RCLK, SCLK outputs held at logic 0
x
1
1
1
1
1
1
Clock counter reset (6)
These lines indicate the reset conditions as required for VGA pass-through.
NOTES:
4. Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer. Register
bit 7 is a don’t care bit.
5. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before
the new clocks are stabilized and running.
6. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = logic 0, and VCLK = logic 1.
7. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.
2.3.2
The TVP3010 VIP has two pixel-data latching modes, allowing for flexibility in the frame-buffer interface
timing. For the pixel port [P(0–31)], data is always latched on the rising edge of LCLK. If auxiliary-control
register (ACR) bit 3 is set to logic 1 (default), the internal circuitry is configured for self-clocked mode. In this
mode, the RCLK or SCLK output of the palette must be used as the timing reference to present data to the
pixel port [P(0–31)]. In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can be a delayed
version of RCLK within the timing requirements of the TVP3010. The self-clocked mode of frame-buffer
latching is similar to the operation of the TLC3407X video interface palette devices.
Frame-Buffer Clocking: Self- or Externally Clocked
The internal TVP3010 blank signal is generated from either VGABL or SYSBL, depending on whether the
VGA port is enabled (multiplex-control register 2 (MCR2) bit 7 = logic 1) or disabled (MCR2 bit 7 = logic 0).
The rising edge of CLK0 is used to latch VGABL when the VGA port is enabled. The falling edge of VCLK
is used to sample and latch the SYSBL input when the VGA port is disabled. When the internal blank
becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when the sampled
SYSBL goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK then is held
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| TVP3010-135 | Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標，伽馬校正，視頻接口調(diào)色板) |
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| TVP3010C | Video Interface Palette |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010-110FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-135MGA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-135MGAB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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