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參數(shù)資料
| 型號： | TVP3010-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(110MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標(biāo)，伽瑪校正貴賓（110MHz的，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 23/100頁 |
| 文件大小： | 571K |
| 代理商： | TVP3010-110 |
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2–9
should be connected to the LCLK input as well as the selected clock input. If the
VGA port is also enabled (MCRB7 = 1), CLK0 is selected as the input clock
independent of the input-clock-selection register setting.
VGA switching can only be performed using a 1:1 multiplexing mode.
Overlay switching can only be performed using a 1:1 multiplexing mode if the pixel
port is set for externally clocked mode. If the pixel port is self-clocked, any of the
multiplex ratios available in Table 2–6 may be used.
If VGA switching is to be performed using externally clocked mode (ACR3 = 0), the
full VGA port frequency of 85 MHz may be utilized provided that the VGA port and
the pixel port are both synchronized to the CLK0 input clock.
If VGA switching is to be performed using self-clocked mode (ACR3 = 1), the
maximum pixel rate cannot exceed 50 MHz. This is because of internal delay from
the CLK0 input to the RCLK output. For external clocked timing, the LCLK input
needs to be enabled on terminal 73 by programming the configuration register
bit 5 to logic 1.
VGA data pipeline delay is adjusted within the TVP3010 VIP depending on whether
self- or externally-clocked frame-buffer interface timing is used (see Section 2.3.2).
If the TVP3010 palette is programmed for self-clocked timing, three additional dot
clock pipeline delays are inserted into the internal VGA data path and into the
internal blanking signal. The additional pipeline delay accounts for the difference
between VGABL or SYSBL and the pixel data inputs [P(0–31)] when used in the
self- and externally-clocked modes. This is so the VGA and pixel-port data remain
synchronous in time when doing auxiliary window, port select, or color-keyed
switching (see Section 2.6). If externally clocked timing is used, the VGA port and
the pixel port are already synchronous since both data and blanking are presented
to the palette during the same CLK0 clock cycle.
VCLK
In Phase
SYSBL
at Input Terminal
LD
Internal Delayed
LCLK = RCLK
Blank
(internal signal
before dot clock
pipeline delay)
Pixel Data
at Input Terminal
SCLK
Latch Last Group
of Pixel Data
Latch First Group of Pixel Data
Latch Last Group
of Pixel Data
Last Group of Pixel Data
1st
Group
2nd
Group
3rd
Group
4th
Group
5th
Group
6th
Group
Figure 2–2. SCLK/VCLK Control Timing
(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3010-135 | Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| TVP3010-170 | Hardware Cursor, GAMMA Correction VIP(170MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| TVP3010-85 | Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| TVP3010C | Video Interface Palette |
| TVP3010M | Video Interface Palette |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010-110FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-135MGA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-135MGAB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3010-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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