685
APPENDIX A DIFFERENCES BETWEEN V
R
4102 AND V
R
4101
A.1 SUMMARY OF DIFFERENCES
Item
V
R
4102
V
R
4101
Cache size
Instruction: 4 Kbytes, data: 1 Kbyte
Instruction: 2 Kbytes, data: 1 Kbyte
ISA
Bus sizing
16-/8-bit dynamic bus sizing
Select 16-/8-bit bus with address spaces
interface
Bus hold
Available
Not available
I/O space
64 Mbytes
4 Mbytes
Memory space
64 Mbytes
4 Mbytes
LCD memory space
Switches between LCD mode and high-speed
memory mode
Supports only LCD mode
Max. DRAM capacity
(EDO type)
32 Mbytes
8 Mbytes
Max. ROM capacity
32 Mbytes
16 Mbytes
DRAM type
16 Mbits, 64 Mbits
16 Mbits
Memory
controller
ROM type
32 Mbits, 64 Mbits
16 Mbits, 32 Mbits
Power-on factor
4 factors
3 factors
DMA controller
Connected to AIU and FIR
Uses a DMA space for each page
Connected to AIU, PIU, KIU, and SIU
Uses a DMA space linearly
Timer, counter
4 channels:
24 bits x 2 (32.768 kHz)
48 bits x 1 (32.768 kHz)
25 bits x 1 (for performance test, TClock)
3 channels:
24 bits x 1 (32.768 kHz)
48 bits x 1 (32.768 kHz)
31 bits x 1 (for performance test, TClock)
Keyboard interface
Supports 64/80/96 keys
Supports up to 64 keys
Audio interface
Supports PCM input/output
On-chip D/A converter
Supports PWM/Buzz output
Touch panel interface
On-chip 10-bit A/D converter
On-chip touch panel controller
External 10/12-bit A/D converter
External touch panel controller
Serial interface
NS16650 compatible x 1
(Max. data rate: 1.152 Mbps)
NEC original x 1
(Max. data rate: 115.2 kbps Max.)
NEC original x 2
(Max. data rate: 115.2 kbps)
Ports for LED lighting
Available
Not available
MODEM interface
On-chip interface supporting software MODEM
(equivalent to PCT288I)
Not available
IrDA interface
FIR (Max. data rate: 4 Mbps)
SIR (Max. data rate: 115.2 kbps)
General-purpose I/O ports
49 Max. (including alternate-function pins)
12 Max.
Clock input
32.768 kHz (input to CG),
18.432 MHz (input to CG),
48 MHz (directly connected to on-chip IrDA
interface)
32.768 kHz (input to CG)
Package
216 pin LQFP, 224-pin FBGA
160 pin LQFP