
C
U
’
s
2
Other Bits (Registers)
–
–
KRM0 (KRM) = 1
–
–
KRM1 (KRM) = 1
–
–
KRM2 (KRM) = 1
–
–
KRM3 (KRM) = 1
PF54 (PF5) = Don
’
t care
PF54 (PF5) = 0
PF54 (PF5) = 0, KRM4 (KRM) = 1
PF55 (PF5) = Don
’
t care
PF55 (PF5) = 0
PF55 (PF5) = 0, KRM5 (KRM) = 1
PFCnx Bit of
PFCn Register
PFC50 = 0
PFC50 = 1
PFC50 = 0
PFC51 = 0
PFC51 = 1
PFC51 = 0
PFC52 = 0
PFC52 = 1
PFC52 = 0
PFC53 = 0
PFC53 = 1
PFC53 = 0
PFC54 = 0
PFC54 = 1
PFC54 = 0
PFC55 = 0
PFC55 = 1
PFC55 = 0
PMCnx Bit of
PMCn Register
PMC50 = 1
PMC50 = 1
PMC50 = 0
PMC51 = 1
PMC51 = 1
PMC51 = 0
PMC52 = 1
PMC52 = 1
PMC52 = 0
PMC53 = 1
PMC53 = 1
PMC53 = 0
PMC54 = 1
PMC54 = 1
PMC54 = 0
PMC55 = 1
PMC55 = 1
PMC55 = 0
PMnx Bit of PMn Register
PM50 = Setting not required
PM50 = Setting not required
PM50 = 1
PM51 = Setting not required
PM51 = Setting not required
PM51 = 1
PM52 = Setting not required
PM52 = Setting not required
PM52 = 1
PM53 = Setting not required
PM53 = Setting not required
PM53 = 1
PM54 = Setting not required
PM54 = Setting not required
PM54 = 1
PM55 = Setting not required
PM55 = Setting not required
PM55 = 1
Pnx Bit of Pn Register
P50 = Setting not required
P50 = Setting not required
P50 = Setting not required
P51 = Setting not required
P51 = Setting not required
P51 = Setting not required
P52 = Setting not required
P52 = Setting not required
P52 = Setting not required
P53 = Setting not required
P53 = Setting not required
P53 = Setting not required
P54 = Setting not required
P54 = Setting not required
P54 = Setting not required
P55 = Setting not required
P55 = Setting not required
P55 = Setting not required
I/O
Input
Output
Input
Input
Output
Input
Output
Output
Input
Input
Output
Input
Output
Output
Input
I/O
Output
Input
Alternate Function
Function Name
TI011
RTP00
KR0
TI50
RTP01
KR1
TO50
RTP02
KR2
SIA0
RTP03
KR3
SOA0
RTP04
KR4
SCKA0
RTP05
KR5
Table 4-28. Settings When Port Pins Are Used for Alternate Functions (2/7)
Pin Name
P50
P51
P52
P53
P54
P55