
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User
’
s Manual U15862EJ3V0UD
361
8.4.4 8-bit PWM output operation
By setting the TMC5n6 bit of 8-bit timer mode control register 5n (TMC5n) to 1, 8-bit timer/event counter 5n
performs PWM output.
Pulses with a duty factor determined by the value set in 8-bit timer compare register 5n (CR5n) are output from the
TO5n pin.
Set the width of the active level of the PWM pulse in the CR5n register. The active level can be selected using the
TMC5n1 bit of the TMC5n register.
The count clock can be selected using timer clock selection register 5n (TCL5n).
PWM output can be enabled/disabled by the TOE5n bit of the TMC5n register.
Caution
The CR5n register rewrite interval must be three or more operation clocks (set by the TCL5n
register).
(1) Basic operation of PWM output
Setting method
<1>
Set each register.
TCL5n register:
CR5n register:
TMC5n register: Stops count operation, selects PWM mode, and leave timer output F/F
unchanged.
Selects the count clock (t).
Compare value (N)
TMC5n1
Active Level Selection
0
Active-high
1
Active-low
Timer output enabled
(TMC5n register = 01000001B or 01000011B)
<2>
When the TCE5n bit of the TMC5n register is set to 1, counting starts.
PWM output operation
<1>
When counting starts, PWM output (output from the TO5n pin) outputs the inactive level until an
overflow occurs.
When an overflow occurs, the active level set by setting method <1> is output. The active level is
output until the value of the CR5n register and the count value of 8-bit timer counter 5n (TM5n)
match.
When the value of the CR5n register and the count value match, the inactive level is output and
continues to be output until an overflow occurs again.
Then, steps <2> and <3> are repeated until counting is stopped.
When counting is stopped by setting TCE5n to 0, PWM output becomes inactive.
<2>
<3>
<4>
<5>
Cycle = 2
8
t, active level width = Nt, duty = N/2
8
: N = 00H to FFH
Remark
n = 0, 1