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CHAPTER 1 INTRODUCTION
User’s Manual U18854EJ2V0UD
23
1.2.2
V850ES/HF3 (
μPD70F3750)
Minimum instruction execution time: 31.25 ns (operating with main clock (fXX) of 32 MHz)
General-purpose registers:
32 bits
× 32 registers
CPU features:
Signed multiplication (16
× 16 → 32): 1 to 2 clocks
Signed multiplication (32
× 32 → 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Memory space:
64 MB of linear address space (for programs and data)
Internal memory:
RAM:
16 KB
Flash memory: 256 KB
Interrupts and exceptions:
Non-maskable interrupts: 2 sources (external: 1, internal: 1)
Maskable interrupts:
50 sources (external: 8, internal: 42)
Software exceptions:
32 sources
Exception trap:
2 sources
I/O lines:
I/O ports:
67
Timer function:
16-bit interval timer M (TMM):
1 channel
16-bit timer/event counter AA (TAA):
5 channels
16-bit timer/event counter AB (TAB):
1 channel
Watch timer:
1 channel
Watchdog timer 2:
1 channel
Serial interface:
Asynchronous serial interface D (UARTD):
2 channels
3-wire variable-length serial interface B (CSIB):
2 channels
I
2C bus:
1 channel
A/D converter:
10-bit resolution: 12 channels
DMA controller:
4 channels (transfer target: on-chip peripheral I/O, internal RAM)
DCU (debug control unit):
JTAG interface
Clock generator:
During main clock or subclock operation
7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
Clock-through mode/PLL mode (
×8)/SSCG mode selectable
Low-speed internal oscillation clock (fRL): 240 kHz (TYP.)
High-speed internal oscillation clock (fRH): 8 MHz (TYP.)
Power-save functions:
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Package:
80-pin plastic LQFP (fine pitch) (12
× 12)