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參數(shù)資料
| 型號： | V55C2128164VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| 中文描述： | 128Mbit低功率SDRAM 2.5伏，第二的TSOP / BGA封裝，8米× 16 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大小： | 591K |
| 代理商： | V55C2128164VB |
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13
V55C2128164V(T/B) Rev. 1.2 August 2002
MOSEL VITELIC
V55C2128164V(T/B)
AC Characteristics
1,2, 3
T
A
= 0 to 70
°
C(Commercial)/-25 to 85
°
C(Extended);V
SS
= 0 V; V
CC
= 2.5 V,V
CCQ
= 1.8V,
t
T
=1 ns
#
Symbol Parameter
Limit Values
Unit Note
-6
-7PC
-7
-8PC
-10
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
1
t
CK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
6
7.5
20
–
–
–
7
7.5
20
–
–
–
7
10
20
–
–
–
8
10
20
–
–
–
10
12
25
–
–
–
ns
ns
ns
2
t
CK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
166
133
50
–
–
–
143
133
50
–
–
–
143
100
50
–
–
–
125
100
50
–
–
–
100
83
40
MHz
MHz
MHz
3
t
AC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
_
_
5.4
5.4
19
–
_
_
5.4
5.4
19
–
_
_
5.4
6
19
–
_
_
6
6
19
–
_
_
7
8
22
ns
ns
ns
2, 4
4
t
CH
Clock High Pulse Width
2.5
–
2.5
–
2.5
–
3
–
3
–
ns
5
t
CL
Clock Low Pulse Width
2.5
–
2.5
–
2.5
–
3
–
3
–
ns
6
t
T
Transition Tim
0.3
1.2
0.3
1.2
0.3
1.2
0.5
10
0.5
10
ns
Setup and Hold Times
7
t
IS
Input Setup Time
1.5
–
1.5
–
1.5
–
2
–
2.5
–
ns
5
8
t
IH
Input Hold Time
0.8
–
0.8
–
0.8
–
1
–
1
–
ns
5
9
t
CKS
Input Setup Time
1.5
–
1.5
–
1.5
–
2
–
2.5
–
ns
5
10
t
CKH
CKE Hold Time
0.8
–
0.8
–
0.8
–
1
–
1
–
ns
5
11
t
RSC
Mode Register Set-up Time
12
–
14
–
14
–
16
–
20
–
ns
12
t
SB
Power Down Mode Entry Time
0
6
0
7
0
7
0
8
0
8
ns
Common Parameters
13
t
RCD
Row to Column Delay Time
12
–
15
–
15
–
20
–
20
–
ns
6
14
t
RP
Row Precharge Time
15
–
15
–
15
–
20
–
20
–
ns
6
15
t
RAS
Row Active Time
40
100K
42
100K
42
100K
45
100k
50
100k
ns
6
16
t
RC
Row Cycle Time
60
–
60
–
60
–
60
–
70
–
ns
6
17
t
RRD
Activate(a) to Activate(b) Command
Period
12
–
14
–
14
–
16
–
20
–
ns
6
18
t
CCD
CAS(a) to CAS(b) Command Period
1
–
1
–
1
–
1
–
1
–
CLK
Refresh Cycle
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