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| 型號： | V55C2128164VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| 中文描述： | 128Mbit低功率SDRAM 2.5伏，第二的TSOP / BGA封裝，8米× 16 |
| 文件頁數(shù)： | 5/44頁 |
| 文件大小： | 591K |
| 代理商： | V55C2128164VB |
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5
V55C2128164V(T/B) Rev. 1.2 August 2002
MOSEL VITELIC
V55C2128164V(T/B)
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Notes:
1.
2.
V = Valid , x = Don’t Care, L = Low Level, H = High Level
CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
These are state of bank designated by BS0, BS1 signals.
Power Down Mode can not entry in the burst cycle.
5. After Deep Power Down mode exit a full new initialization of memory device is mandatory
3.
4.
Operation
Device
State
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM
A0-9,
A11
A10
BS0
BS1
Row Activate
Idle
3
H
X
L
L
H
H
X
V
V
V
Read
Active
3
H
X
L
H
L
H
X
V
L
V
Read w/Autoprecharge
Active
3
H
X
L
H
L
H
X
V
H
V
Write
Active
3
H
X
L
H
L
L
X
V
L
V
Write with Autoprecharge
Active
3
H
X
L
H
L
L
X
V
H
V
Row Precharge
Any
H
X
L
L
H
L
X
X
L
V
Precharge All
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set
Idle
H
X
L
L
L
L
X
V
V
V
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry
Idle
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit
Idle
(Self Refr.)
L
H
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Entry
Idle
Active
4
H
L
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Exit
Any
(Power
Down)
L
H
H
X
X
X
X
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
Deep Pwoer Down Entry
Idle
H
L
L
H
H
L
H
X
X
X
Deep Pwoer Down Exit
Deep power-
Down
L
H
X
X
X
X
H
X
X
X
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