- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359326 > V55C2128164VB (Mosel Vitelic, Corp.) 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 PDF資料下載
參數(shù)資料
| 型號(hào)： | V55C2128164VB |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| 中文描述： | 128Mbit低功率SDRAM 2.5伏，第二的TSOP / BGA封裝，8米× 16 |
| 文件頁數(shù)： | 4/44頁 |
| 文件大?。?/td> | 591K |
| 代理商： | V55C2128164VB |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
4
V55C2128164V(T/B) Rev. 1.2 August 2002
MOSEL VITELIC
V55C2128164V(T/B)
Description
The V55C2128164V(T/B) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16. The
V55C2128164V(T/B) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock
All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-
ternally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A11
Input
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
8M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
—
Selects which bank is to be active.
DQx
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
VCC, VSS
Supply
Power and ground for the input buffers and the core logic.
VCCQ
VSSQ
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V55C2128164VT | 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| V55C2128164V | 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| V56CH8 | Surface Mount Varistors - Transient Voltage Surge Suppressor |
| V56MA2B | Varistor Products - Axial Lead |
| V56RA16 | Varistor Products - Low Profile |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V55C2128164VT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16 |
| V55C2256164VB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16 |
| V55HD | 制造商:Bugera 功能描述:55 WATT GUITAR AMPLIFIER 2 CHANNEL TUBE HEAD |
| V55MLA0402LN | 制造商:LITTELFUSE 制造商全稱:Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
| V55MLA0402N | 制造商:LITTELFUSE 制造商全稱:Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。