參數(shù)資料
型號: V55C2128164VB
廠商: Mosel Vitelic, Corp.
英文描述: 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16
中文描述: 128Mbit低功率SDRAM 2.5伏,第二的TSOP / BGA封裝,8米× 16
文件頁數(shù): 15/44頁
文件大?。?/td> 591K
代理商: V55C2128164VB
15
V55C2128164V(T/B) Rev. 1.2 August 2002
MOSEL VITELIC
V55C2128164V(T/B)
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Burst Write Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Power Down Mode
13. Self Refresh (Entry and Exit)
14. Auto Refresh (CBR)
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