參數(shù)資料
型號(hào)： V55C2128164VB
廠商： Mosel Vitelic, Corp.
英文描述： 128Mbit LOW-POWER SDRAM 2.5 VOLT, TSOP II / BGA PACKAGE 8M X 16
中文描述： 128Mbit低功率SDRAM 2.5伏，第二的TSOP / BGA封裝，8米× 16
文件頁(yè)數(shù)： 9/44頁(yè)
文件大?。?/td> 591K
代理商： V55C2128164VB
9
V55C2128164V(T/B) Rev. 1.2 August 2002
MOSEL VITELIC
V55C2128164V(T/B)
Burst Length and Sequence:
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one t
RC
delay
is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t
DQZ
). It also provides
a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
ited (DQM Write Mask Latency t
DQW
= zero clocks).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the
Read with Auto-Precharge
function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, two clocks for CAS laten-
cies 3 and three clocks for CAS latencies 4. If CA10
is high when a Write Command is issued, the
Write
Burst
Length
Starting Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
Full Page nnn Cn, Cn+1, Cn+2 Not supported
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