參數(shù)資料
型號: V59C1G01408QAJ37E
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 256M X 4 DDR DRAM, 0.5 ns, PBGA68
封裝: ROHS COMPLIANT, FBGA-68
文件頁數(shù): 26/79頁
文件大?。?/td> 1029K
代理商: V59C1G01408QAJ37E
32
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Burst Write Operation : RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
NOP
WRITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
Tm
Tn
WL = RL-1 = 2
BW322
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tWR
Completion of
the Burst Write
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
CK, CK
Burst Write followed by Burst Read : RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4
NOP
READ A
Post CAS
BWBR
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
AL=2
CL=3
NOP
tWTR
T0
T2
T1
T3
T4
T5
T6
T7
T8
T9
Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6
DQS,
DQS
WL = RL - 1 = 4
RL=5
CK, CK
The minimum number of clocks from the burst write command to the burst read command is
(CL - 1) +BL/2 + tWTR
where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write
recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers
in the array.
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