參數(shù)資料
型號(hào): V59C1G01408QAJ37E
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: 256M X 4 DDR DRAM, 0.5 ns, PBGA68
封裝: ROHS COMPLIANT, FBGA-68
文件頁(yè)數(shù): 60/79頁(yè)
文件大?。?/td> 1029K
代理商: V59C1G01408QAJ37E
63
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
OCD de fault characteristics
Description
Parameter
Min
Nom
Max
Unit
Notes
Output impedance
See full strength default driver characteristics
1
Output impedance step size for
OCD calibration
0.5
6
Pull-up and pull-down mismatch
0
4
1,2,3
Output slew rate
Sout
1.5
5
V/ns
1,4,5,7,8,9
NOTE 1
Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing,
voltage, and slew rate are no longer applicable if OCD is changed from default settings.
NOTE 2
Impedance measurement condition for output source dc current: VDDQ = 1.7 V; VOUT = 1420 mV; (VOUT-
VDDQ)/Ioh must be less than 23.4
for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condi-
tion for output sink dc current: VDDQ = 1.7 V; VOUT = 280 mV; VOUT/Iol must be less than 23.4
for values of VOUT
between 0 V and 280 mV.
NOTE 3
Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.
NOTE 4
Slew rate measured from vil(ac) to vih(ac).
NOTE 5
The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured
from AC to AC. This is guaranteed by design and characterization.
NOTE 6
This represents the step size when the OCD is near 18
at nominal conditions across all process corners/variations
and represents only the DRAM uncertainty. A 0
value (no calibration) can only be achieved if the OCD impedance is 18
+/-
0.75
under nominal conditions.
NOTE 7
DRAM output slew rate specification applies to 667 MT/s speed bins.
NOTE 8
Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in
tDQSQ and tQHS specification.
NOTE 9
DDR2 SDRAM output slew rate test load is defined in General Note 3 of the AC Timing specification Table.
AC & DC operating conditions (cont'd)
相關(guān)PDF資料
PDF描述
V59C1G01408QAJ37I 256M X 4 DDR DRAM, 0.5 ns, PBGA68
V5D010EB4D SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.5A, 125VDC, 4.4mm, PANEL MOUNT
V5F110CB SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, PANEL MOUNT
V5PNF CABLE TERMINATED, FEMALE, N CONNECTOR, THREAD-IN STUB SELF-FLARE
V5T110TB3 SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.6A, 125VDC, 2.4mm, PANEL MOUNT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
V5A010CB 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER
V5A010CB 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER
V5A010CB4D 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
V5A010CB4D 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER
V5A010CB4E 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER