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參數(shù)資料
| 型號(hào)： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁(yè)數(shù)： | 27/79頁(yè) |
| 文件大?。?/td> | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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33
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
NOP
DIN A0 DIN A1 DIN A2 DIN A3
WRITE A
Post CAS
WL = RL - 1 = 4
WRITE B
Post CAS
DIN B0 DIN B1 DIN B2 DIN B3
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
SBR
DQS,
DQS
CK, CK
Seamless Burst Write Operation: RL=5, WL=4, BL=4
The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks.
This operation is allowed regardless of same or different banks as long as the banks are activated.
NOP
WRITE A
WL = RL - 1 = 2
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
SBW_BL8
DQS,
DQS
WRITE B
DIN A0 DIN A1 DIN A2 DIN A3 DIN A4 DIN A5 DIN A5 DIN A7 DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN
CK, CK
Seamless Burst Write Operation: RL=3, WL=2, BL=8, noninterrupting
The seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every
BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks
are activated.
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| V59C1G01408QAJ37I | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
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