參數(shù)資料
型號(hào)： V59C1G01408QAJ37E
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 256M X 4 DDR DRAM, 0.5 ns, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁數(shù)： 54/79頁
文件大?。?/td> 1029K
代理商： V59C1G01408QAJ37E
58
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.
NOTE 1
Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level
applied to the device under test.
NOTE 2
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min
for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
NOTE 3
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the pos-
itive transitions and VIH(ac) to VIL(ac) on the negative transitions.
Input DC logic level
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(dc)
dc input logic HIGH
VREF + 0.125
VDDQ + 0.3
V
VIL(dc)
dc input logic LOW
- 0.3
VREF - 0.125
V
Input AC logic level
Symbol
Parameter
DDR2-667, 800, 1066
Units
Min.
Max.
V
IH (ac)
ac input logic HIGH
VREF + 0.200
-
V
IL (ac)
ac input logic LOW
-VREF - 0.200
V
AC input test conditions
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 x VDDQ
V1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
VM =
2 x Vm
VDDQ
x 100%
- 1
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VSWING(MAX)
TR
TF
VREF - VIL(ac) max
TF
Falling Slew =
Rising Slew =
VIH(ac) min - VREF
TR
AC input test signal waveform
AC & DC operating conditions (cont'd)
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