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參數(shù)資料
| 型號： | VPC3200A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Comb Filter Video Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 22/78頁 |
| 文件大?。?/td> | 1245K |
| 代理商： | VPC3200A |
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VPC 323xD, VPC 324xD
ADVANCE INFORMATION
22
Micronas
2.11. Video Sync Processing
Fig. 2–18 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is
separated by a slicer; the sync phase is measured. A
variable window can be selected to improve the noise
immunity of the slicer. The phase comparator mea-
sures the falling edge of sync, as well as the integrated
sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it
thus counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/mini-
mum of the video signal. This information is processed
by the FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is
integrated. The FP uses the integrator value to derive
vertical sync and field information.
The information extracted by the video sync process-
ing is multiplexed onto the hardware front sync signal
(FSY) and is distributed to the rest of the video pro-
cessing system. The format of the front sync signal is
given in Fig. 2–19.
The data for the vertical deflection, the sawtooth, and
the East-West correction signal is calculated by the
VPC 32xx. The data is buffered in a FIFO and trans-
ferred to the back-end IC DDP 3300A by a single wire
interface.
Frequency and phase characteristics of the analog
video signal are derived from PLL1. The results are fed
to the scaler unit for data interpolation and orthogonal-
ization and to the clock synthesizer for line-locked
clock generation. Horizontal and vertical syncs are
latched with the line-locked clock.
Fig. 2–18:
Sync separation block diagram
Fig. 2–19:
Front sync format
phase
comparator
&
lowpass
counter
frontend
timing
front sync
skew
vblank
field
lowpass
1 MHz
&
syncslicer
horizontal
sync
separation
vertical
sync
separation
FIFO
Sawtooth
Parabola
Calculation
video
input
front
sync
generator
vertical
serial
data
vertical
E/W
sawtooth
clamping, colorkey, FIFO_write
PLL1
clamp &
signal
meas.
clock
synthesizer
syncs
clock
H/V syncs
F1
input
analog
video
FSY
F1
F0
skew
LSB
skew
MSB
not
F
V
(not in scale)
F0 reserved
0 = field 1
1 = field 2
F: field #
0 = off
1 = on
V: vertical sync
Parity
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPC3200APSGP | 制造商:MICRONAS 功能描述:New |
| VPC3201A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Comb Filter Video Processor |
| VPC3205C | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Comb Filter Video Processor |
| VPC3210A | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Comb Filter Video Processor |
| VPC3210B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
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