![](http://datasheet.mmic.net.cn/220000/VPC3200A_datasheet_15512207/VPC3200A_41.png)
ADVANCE INFORMATION
VPC 323xD, VPC 324xD
Micronas
41
h’14e
Status of automatic standard recognition
bit[0]
1
error of the vertical standard (neither 50 nor 60 Hz)
bit[1]
1
detected standard is disabled
bit[2]
1
search active
bit[3]
1
search terminated, but failed
bit[3:0]
0000 all ok
0001 search not started, because vwin error detected
(no input or SECAM L)
0010 search not started, because detected vert. standard
not enabled
x1x0 search started and still active
1x00 search failed (found standard not correct)
1x10 search failed, (detected color standard not enabled)
0
ASR_STATUS
VWINERR
DISABLED
BUSY
FAILED
h’21
Input select:
writing to this register will also initialize the standard
bit[1:0]
luma selector
VIN3
VIN2
VIN1
VIN4
chroma selector
VIN1/CIN
IF compensation
off
6 dB/Okt
12 dB/Okt
10 dB/MHz only for SECAM
chroma bandwidth selector
narrow
normal
broad
wide
adaptive/fixed SECAM notch filter
enable luma lowpass filter
hpll speed
no change
terrestrial
vcr
mixed
status bit, write 0, this bit is set to 1 to indicate
operation complete.
00
01
10
11
bit[2]
0/1
bit[4:3]
00
01
10
11
bit[6:5]
00
01
10
11
0/1
0/1
bit[8]
bit[10:9]
00
01
10
11
bit[11]
0
1
0
2
0
0
3
INSEL
VIS
CIS
IFC
CBW
FNTCH
LOWP
HPLLMD
h’22
picture start position: This register sets the start point of active video
and can be used e.g. for panning. The setting is updated when ‘sdt’
register is updated or when the scaler mode register ‘scmode’ is writ-
ten.
0
SFIF
h’23
luma/chroma delay adjust. The setting is updated when ‘sdt’ register
is updated.
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ... –7
0
LDLY
h’29
helper delay register (PAL+ mode only)
bit[11:0]
delay adjust for helper lines adjustable from
–96...96, 1 step corresponds to 1/32 clock
0
HLP_DLY
FP Sub-
address
Function
Default
Name