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| 型號(hào)： | VPC3200A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Comb Filter Video Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 30/78頁(yè) |
| 文件大小： | 1245K |
| 代理商： | VPC3200A |
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VPC 323xD, VPC 324xD
ADVANCE INFORMATION
30
Micronas
3. Serial Interface
3.1. I
2
C-Bus Interface
Communication between the VPC and the external
controller is done via I
2
C-bus. The VPC has an I
2
C-bus
slave interface and uses I
2
C clock synchronization to
slow down the interface if required. The I
2
C-bus inter-
face uses one level of subaddress: one I
2
C-bus
address is used to address the IC and a subaddress
selects one of the internal registers. For multi
VPC32xxD applications the following three I
2
C-bus
chip addresses are selectable via I2CSEL pin:
The registers of the VPC have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
Figure 3–1 shows I
2
C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip
address with read command set.
3.2. Control and Status Registers
Table 3–1 gives definitions of the VPC control and sta-
tus registers. The number of bits indicated for each
register in the table is the number of bits implemented
in hardware, i.e. a 9-bit register must always be
accessed using two data bytes but the 7 MSB will be
‘don’t care’ on write operations and ‘0’ on read opera-
tions. Write registers that can be read back are indi-
cated in Table 3–1.
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 3–1.
Fig. 3–1:
I
2
C-bus protocols
A6
A5
A4
A3
A2
A1
A0
R/W I2CSEL
1
0
0
0
1
1
1
1/0
V
SUP
1
0
0
0
1
1
0
1/0
VRT
1
0
0
0
1
0
0
1/0
GND
P
S
1
0
SDA
SCL
S
S
1000 111
1000 111
W Ack
Ack
W
0111 1100
0111 1100
Ack
Ack
S
1 or 2 byte Data
1000 111
R
high byte Data
low byte Data
P
W
R
Ack
Nak
S
P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Ack
Nak P
I
2
C write access
subaddress 7c
I
2
C read access
subaddress 7c
Ack
S
1000 111
W Ack
FPWR
Ack
P
byte high
send FP-address-
Ack
byte low
send FP-address-
Ack
S
1000 111
W Ack
FPDAT
Ack
P
byte high
send data-
Ack
byte low
send data-
Ack
I
2
C write access
to FP
S
1000 111
W Ack
FPRD
Ack
P
byte high
send FP-address-
Ack
byte low
send FP-address-
Ack
S
1000 111
W Ack
FPDAT
Ack
P
byte high
receive data-
receive data-
Ack
byte low
Nak
I
2
C read access
to FP
S
1000 111
R Ack
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