
ADVANCE INFORMATION
VPC 323xD, VPC 324xD
Micronas
43
DVCO
h’f8
crystal oscillator center frequency adjust, –2048 ... 2047
–720
DVCO
h’f9
crystal oscillator center frequency adjustment value for line-lock
mode, true adjust value is DVCO – ADJUST.
For factory crystal alignment, using standard video signal: disable
autolock mode, set DVCO = 0, set lock mode, read crystal offset from
ADJUST register and use negative value for initial center frequency
adjustment via DVCO.
read only
ADJUST
h’f7
crystal oscillator line-locked mode, lock command/status
write: 100
0
read: 0
>2047
enable lock
disable lock
unlocked
locked
0
XLCK
h’b5
crystal oscillator line-locked mode, autolock feature. If autolock is
enabled, crystal oscillator locking is started automatically.
bit[11:0]
threshold, 0:autolock off
400
AUTOLCK
FP Status Register
h’12
general purpose control bits
bit[2:0]
bit[3]
bit[8:4]
bit[9]
bit[11:10]
to enable vertical free run mode set vfrc to 1 and dflw to 0
reserved, do not change
vertical standard force
reserved, do not change
disable flywheel interlace
reserved, do not change
0
1
VFRC
DFLW
h’13
standard recognition status
bit[0]
1
bit[1]
1
bit[2]
1
bit[3]
1
bit[4]
1
bit[5]
1
bit[6]
1
bit[7]
1
bit[8]
1
bit[9]
1
bit[12:10]
vertical lock
horizontally locked
no signal detected
color amplitude killer active
disable amplitude killer
color ident killer active
disable ident killer
interlace detected
no vertical sync detection
spurious vertical sync detection
reserved
–
ASR
h’14
input noise level, available only for VPC 323xC
read only
NOISE
h’cb
number of lines per field, P/S: 312, N: 262
read only
NLPF
h’15
vertical field counter, incremented per field
read only
VCNT
h’74
measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC)
read only
SAMPL
h’31
measured burst amplitude
read only
BAMPL
h’f0
firmware version number
bit[7:0]
bit[11:8]
internal revision number
firmware release
hardware id see I
2
C register h’9f
read only
–
FP Sub-
address
Function
Default
Name