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參數(shù)資料
| 型號： | VPX3214C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 20/80頁 |
| 文件大?。?/td> | 752K |
| 代理商： | VPX3214C |
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PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
20
3.2.3. Scan Mode
In the Scan Mode, the HREF and VREF signals are al-
ways generated by free running hardware. They are
therefore completely decoupled from the analog input.
The output video data is always suppressed.
The purpose of the Scan Mode is to allow the external
controller to freely switch between the analog inputs
while searching for the presence of a video signal. In-
formation regarding the video (standard, source, etc...)
can be queried via I
2
C read.
In the Scan Mode, the video line standard of the VREF
and HREF signals can be changed via I
2
C command.
The transition always occurs at the first frame boundary
after the I
2
C command is received. Fig. 3–4, below,
demonstrates the behavior of the VREF signal during
the transition from the 525/60 system to the 625/50 sys-
tem (the width of the vertical reference pulse is exagger-
ated for illustration).
3.2.4. Transition Behavior
During normal operation, the timing characteristics of
the input video can change in response to a number of
phenomena: power up/reset, unplugging of the video
jack, switching between selected video inputs, etc... The
effect of these changes on the video timing signals is de-
pendent on the current operational mode. Table 3–1
summarizes this dependency.
In the Forced Mode, it can often occur that the VPX must
resynchronize to an analog input signal after a period in
free running sync generation. In such a case, it is likely
that the internal sync generators are out of phase with
the time base of the analog input. Maintaining a stable
sync signal requires that the transition between time
bases occur over several field periods.
Fig. 3–5 illustrates the transition between an internal
free running vertical sync and a vertical sync of the ana-
log input. The top two lines in this figure show the vertical
time base of the analog input signal relative to that of the
VREF generated from the free running clock. Both the
analog input and free running syncs conform to the
same line standard, but the field polarities are out of
phase and the offset between field syncs (given by
Φ
error
) is greater than the allowed 20 lines.
In the Forced Mode, vertical resynchronization takes
place on field boundaries (as opposed to frame bound-
aries) and begins immediately after the appearance of
the analog input. In the first field after the appearance of
this analog video, the period between VREF pulse is
shortened by 20 lines (
Φ
rec–)
and the field polarity of the
VREF is repeated. For each subsequent field, the phase
error is reduced by
Φ
rec–
until the two signals are again
in phase.
Because the resynchronization occurs on field bound-
aries and because the internally generated sync can be
either lengthened or shortened, the maximum value of
Φ
error
is 313/2
157 lines. With a maximum correction
of 20 lines per field, field locking requires a maximum of
8 fields.
VREF
f
odd
f
odd
f
even
f
even
f
odd
time
33.367 ms
16.683 ms
40.0 ms
20.0 ms
I
2
C Command to
switch video timing standard
Selected timing standard
becomes active
(525/60)
(625/50)
Fig. 3–4:
Transition between timing standards
相關PDF資料 |
PDF描述 |
|---|---|
| VPX3224D | Video Pixel Decoders |
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3214C(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3214C(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3216B(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
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