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| 型號： | VPX3214C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 75/80頁 |
| 文件大?。?/td> | 752K |
| 代理商： | VPX3214C |
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VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
75
6.6.14. Characteristics, Enable/Disable of Output
Signals
In order to enable the output pins of the VPX to achieve
the high impedance/tristate mode, various controls have
been implemented. The following paragraphs give an
overview of the different tristate modes of the output sig-
nals. It is valid for all output pins, except the XTAL2
(which is the oscillator output) and the VRT pin (which is
an analog reference voltage).
BS (Boundary-Scan) Mode:
The tristate control by the test access port TAP for
boundary-scan has the highest priority. Even if the TAP-
controller is in the EXTEST or CLAMP mode, the tristate
behavior is only defined by the state of the different
boundary scan registers for enable control. If the TAP
controller is in HIGHZ mode, then all output pins are in
tristate mode independently of the state of the different
boundary scan registers for enable control.
RESET State:
If the TAP-controller is not in the EXTEST mode, then the
RESET-state defines the state of all digital outputs. The
only exception is made for the data output of the bound-
ary scan interface TDO. If the circuit is in reset condition
(RES = 0), then all output interfaces are in tristate mode.
I
2
C Control:
The tristate condition of groups of signals can also be
controlled by setting the I
2
C-Register F2
hex
. If the circuit
is neither in EXTEST mode nor RESET state, then the
I
2
C-Register F2
hex
defines whether the output is in tris-
tate condition or not. The I
2
C-Register #F1 uses differ-
ent bits for different groups of outputs (see “I
2
C-Register
Table”).
Output Enable Input OE:
The output enable signal OE only effects the video out-
put ports. If the previous three conditions do not cause
the output drivers to go into high impedance mode, then
the OE signal defines the driving conditions of the video
data ports.
EXTEST
RESET
I
2
C
OE#
Driver Stages
active
–
–
–
Output driver stages are defined by the state of the different
boundary-scan enable registers.
inactive
active
–
–
Output drivers are in high impedance mode.
inactive
inactive
= 0
–
Output drivers are in high impedance mode. PIXCLK is working.
inactive
inactive
= 1
–
Output drivers HREF, VREF, PREF, FE, HF are working.
inactive
inactive
= 1
= 1
Output drivers of ALPHA, A[7:0], B[7:0], and C[7:0] are in high impedance
mode.
inactive
inactive
= 1
= 0
Outputs ALPHA, A[7:0], B[7:0], and C[7:0] are working
Remark:
EXTEST mode is an instruction conforming to the standard for Boundary-Scan Test IEEE 1149.1 – 1990
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| VPX3214C(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3214C(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3216B(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
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