參數(shù)資料
型號: VPX3214C
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁數(shù): 53/80頁
文件大?。?/td> 752K
代理商: VPX3214C
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
53
6.3. Pin Descriptions (Pin Numbers for PLCC44)
Pins 44, 1 – JTAG Input Pins TMS, TDI (Fig. 6–6)
Mode Select and Data Input signal for the JTAG Test Ac-
cess Port (TAP). These inputs have small pull-ups and
input stages with Schmitt trigger characteristics.
Pin 2 – JTAG Input Pin TCK (Fig. 6–5)
Clock input pin for JTAG Test Access Port (TAP). This in-
put has an input stage with Schmitt trigger characteris-
tics and no pull-up.
Pin 3 – JTAG Output Pin TDO (Fig. 6–8)
Data output for JTAG Test Access Port (TAP), and output
pin for the ALPHA key signal, if the TAP is in Test-Logic-
Reset state. The output circuit belongs to the character-
istics of TTL output driver type B.
Pins 4 to 6 – Reference Signals HREF, VREF, and PREF
(Fig. 6–8)
These signals are internally generated sync signals.
Their output characteristics belong to the output driver
type B.
Pins 7 to 10, 14 to 17 – Video Port A (Fig. 6–8)
The output characteristics of these pins belong to the
characteristics of output driver type A.
Pin 11 – Supply Voltage, Pad Circuitry PVDD
Pin 12 – Pixel Clock PIXCLK (Fig. 6–9)
This signal is either input or output depending on the se-
lected mode. In synchronous mode it has the character-
istics of TTL output driver type A. In asynchronous mode
it has TTL Schmitt trigger input characteristics. PIXCLK
is the reference clock for the video data transmission
ports A[7:0] and B[7:0]. Moreover, the state of the
PIXCLK signal at the inactive going edge of RES deter-
mines which I
2
C_INIT table will be loaded (see section
4.9.)
Pin 13 – Ground, Pad Circuitry PVSS
Pin 18 – Output Enable Input Signal (Fig. 6–5)
The output enable input signal has TTL Schmitt trigger
input characteristics. It controls the tristate condition of
both video ports.
Pins 19, 20 – HF, FE, (Fig. 6–8)
These pins have different functionality depending on
which video data output mode is selected. The output
circuits belong to the characteristics of TTL output driver
type A.
Pins 21 to 28 – Video Port B (Fig. 6–8)
The output characteristics of these pins belong to the
characteristics of TTL output driver type B.
Pin 29 – I
2
C Data SDA (Fig. 6–7)
This pin connects to the I
2
C-bus data line.
Pin 30 – I
2
C Clock SCL (Fig. 6–7)
This pin connects to the I
2
C-bus clock line.
Pin 31 – Reset Input RES (Fig. 6–5)
A low level on this pin resets the circuit.
Pin 32 – Ground, Digital Circuitry VSS
Pin 33 – Supply Voltage, Digital Circuitry VDD
Pins 34, 35 – XTAL1 Crystal Input and XTAL2 Crystal
Output (Fig. 6–11)
These pins are connected to a 20.25 MHz crystal oscilla-
tor which is digitally tuned by integrated shunt capaci-
tances. An external clock can be fed into XTAL1. In this
case clock frequency adjustment must be switched off.
Pin 36 – Supply Voltage, Analog Circuitry AVDD
Pin 37 – Chroma Input CIN (Fig. 6–10, Fig. 6–14)
This pin is connected to the S-VHS chroma signal. A re-
sistive divider is used to bias the input signal to the
middle of the converter input range. CIN can only be
connected to the chroma (Video 2) AD converter. The
signal must be AC-coupled.
Pin 38 – Ground, Analog Front-end AVSS
Pins 39, 40, 42 – Video Input 1–3 VIN1,VIN2,VIN3
(Fig. 6–12)
These are the analog video inputs. A CVBS, S-VHS
luma signal is converted using the luma (Video 1) AD
converter. The VIN1 input can also be switched to the
chroma (Video 2) ADC. The input signal must be AC-
coupled.
Pin 41 – Reference Voltage Top VRT (Fig. 6–13)
Via this pin, the reference voltage for the AD converters
is decoupled. The pin is connected with 10
μ
F/47 nF to
the Signal Ground Pin.
Pin 43 – Signal Ground for Analog Input ISGND
This is the high-quality ground reference for the video
input signals.
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