參數(shù)資料
型號: VPX3214C
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁數(shù): 37/80頁
文件大?。?/td> 752K
代理商: VPX3214C
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 216 B, VPX 3214 C
MICRONAS INTERMETALL
37
FP-Register Table
FP Reg.
Address
Number
of Bits
Mode
Function
Name
Control Word
F0
12
w r
Register for control and latching
CMDWD
w
bit [0] :
Transport Rate
0
1
20.25 MHz.
13.5 MHz.
settr
w
bit [1] :
Latch Transport Rate
1
latch (reset automatically)
lattr
w
bit [3:2] :
Sync timing mode
0 0
0 1
1 x
Open
Forced
Scan
settm
w
bit [4] :
Latch Timing Mode
1
latch (reset automatically)
lattm
w
bit [5] :
Latch Window #1
1
latch (reset automatically)
latwin1
w
bit [6] :
Latch Window #2
1
latch (reset automatically)
latwin2
wr
bit[8] :
Odd/Even mode
0
1
toggles always
follows odd/even property of input video signal
disoef
bit [11:9]
reserved (must be set to zero)
Info Word
InfoWord
F1
12
r
Internal status register do not overwrite
bit [2:0] :
reserved
bit [5:3] :
Current active TV standard
x x x
see table of 3-bit code of TV standards
acttv
bit [6] :
Line Standard of currently active TV standard
0
525 / 60
1
625 / 50
actls
bit [11:7]
reserved
The control register modes are
– w: write/read register
– r:
read-only register
– A: register or register field has function only in VPX 3220 A
The mnemonics used in the Intermetall VPX demo software are given in the last column.
相關(guān)PDF資料
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VPX3224D Video Pixel Decoders
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