PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
50
6.2. Pin Connections and Short Descriptions
NC = not connected; leave vacant
LV = if not used, leave vacant
S.T.B. = shorted to BAGNDI if not used
DVSS = if not used, connect to DVSS
X = obligatory; connect as described in circuit diagram
AHVSS = connect to AHVSS
Pin No.
Connection
(if not used)
Pin Name
Type
Short Description
PLCC
44-pin
PTQFP
44-pin
1
39
NC
TDI
IN
Boundary-Scan-Test Data Input
2
40
NC
TCK
IN (+Pull-
up)
Boundary-Scan-Test Clock Input
3
41
NC
TDO
ALPHA
LLC2
OUT
OUT
OUT
Boundary-Scan-Test Data Output if TAP is
active (see remarks on Boundary-Scan
Test)
If Test Access Port (TAP) is in Test-Logic-
Reset State: Alpha Key Signal (I
2
C Reg.
EA
hex
bit[3] = 0)
If Test Access Port (TAP) is in Test-Logic-
Reset State: LLC/2 = 13 MHz clock signal
(I
2
C Reg. EA
hex
bit[3] = 1)
4
42
NC
HREF
OUT
Horizontal Reference
5
43
NC
VREF
OUT
Vertical Reference
6
44
NC
PREF
ODD/EVEN
I
2
C-ADDR
OUT
OUT
IN
Programmable Interrupt
ODD/EVEN Frame Identifier
I
2
C-Initialization Control by positive edge of
RES:
PREF = 0 : I
2
C device address 0
PREF = 1 : I
2
C device address 1
(for more information see I
2
C description)
7
1
NC
A7
OUT
Port 1 – Video Data Output
8
2
NC
A6
OUT
Port 1 – Video Data Output
9
3
NC
A5
OUT
Port 1 – Video Data Output
10
4
NC
A4
OUT
Port 1 – Video Data Output
11
5
PVDD
SUPPLY
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12
6
NC
PIXCLK
I
2
C-INIT
OUT
IN
IN
Pixel Clock I/O Synchronous mode
Asynchronous mode
I
2
C-Initialization Control by positive edge of
RES:
PIXCLK = 0 : I
2
C ROM table 0
PIXCLK = 1 : I
2
C ROM table 1
(for more information see I
2
C description)
13
7
PVSS
SUPPLY
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