VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
67
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
PIXCLK: Asynchronous Mode
V
IL
Input Voltage LOW
–0.5
0.8
V
V
IH
Input Voltage HIGH
for input pin PIXCLK
2.0
–
PVDD +
0.3
V
V
TRHL
Trigger Level at Transition High to Low
1.2
V
V
TRLH
Trigger Level at Transition Low to High
1.6
V
Φ
CYCL
Cycle Time
35
ns
Φ
H
Minimum Pulse width ’HIGH’
–
–
ns
Φ
L
Minimum Pulse width ’LOW’
–
–
ns
t
D
Delay PIXCLK(input) to
A [7:0]
B [7:0]
neg. edge of FE
11
20
20
ns
ns
ns
pos. edge of HF
ALPHA
tbd
20
ns
ns
A special PVDD, PVSS supply is used only to support the digital output pins. This means, inherently, that in case of
tristate conditions, external sources should not drive these signals above the voltage PVDD which supplies the output
pins.
All timing specifications are based on the following assumptions:
– the load capacitance of the fast pins (output driver type A) is C
A
= 30 pF,
– the load capacitance of the remaining pins (output driver type B) is C
B
= 50 pF;
– no static currents are assumed;
– the driving capability of the pads is STR = 4, which means that 5 of 8 output drivers are enabled.
The typical case specification relates to:
– the ambient temperature is T
A
= 25
°
C, which relates to a junction temperature of T
J
= 70
°
C;
– the power supply of the pad circuits is PVDD = 3.3 V, and the power supply of the digital parts is VDD = 5.0 V.
The best case specification relates to:
– a junction temperature of T
J
= 0
°
C;
– the power supply of the pad circuits is PVDD = 3.6 V, and the power supply of the digital parts is VDD = 5.25 V.
The worst case specification relates to:
– a junction temperature of T
J
= 125
°
C;
– the power supply of the pad circuits is PVDD = 3.0 V, and the power supply of the digital parts is VDD = 4.75 V.
Rise times are specified as a transition between 0.6 V to 2.4 V. Fall times are defined as a transition between 2.4 V to
0.6 V.