參數(shù)資料
型號(hào): VPX3214C
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁(yè)數(shù): 26/80頁(yè)
文件大?。?/td> 752K
代理商: VPX3214C
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
26
3.4.2. Asynchronous Output
In the asynchronous mode, data is strobed from the VPX
by an external clock supplied to the PIXCLK pin. A
32-pixel FIFO buffers the video samples for transfer.
Two FIFO status signals (HF and FE) arbitrate the trans-
fer. The ‘half full’ signal (HF) indicates that the number
of samples present in the FIFO has exceeded some pro-
grammable threshold (defined over the range of 0
The FE signal indicates that the FIFO is empty.
31).
Some implementations of the asynchronous mode re-
quire a more detailed understanding of the rates at
which the data is written to and read from the 32 pixel
output FIFO. On the input side of the FIFO, sampled vid-
eo data from the VPX-core arrives as a continuous burst
with a pixel rate equal to that of the transport clock
(20 MHz or 13 MHz burst rate).
On the output side, the rate at which the FIFO is emptied
is dependent on the speed of the PIXCLK and the se-
lected clocking mode. In the asynchronous mode, the
PIXCLK is always a single-edge clock.
Port Data
7
8
7
7
6
6
5
2
1
FIFO
fullness level
PIXCLK=2*internal
transfer rate
HF
if full-level is 8
FE
3
2
2
1
1
0
1
0
1
2
Fig. 3–12:
Timing for Asynchronous Output
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