PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
28
Figure 4–1 shows I
2
C bus protocols for read and write
operations of the interface. The read operation requires
an extra start condition after the subaddress and repeti-
tion of the read chip address, followed by the read data
bytes. The following protocol examples use device ad-
dress hex 86/87.
Fig. 4–1:
I
2
C bus protocol
(MSB first)
SDA
SCL
1
0
S
P
4.5. FP Control and Status Registers
In addition to the I
2
C subaddress space, a second class
of address space is defined for direct communication
with the on-board
μ
controller. These registers are ac-
cessed via indirect addressing through I
2
C registers
(see Fig. 4–2).
Due to the internal architecture of the VPX 3220 A, the
IC cannot react immediately to all I
2
C requests which in-
teract with the embedded processor (FP). The maxi-
mum response timing is approx. 20 ms (one TV field) for
the FP processor if TV standard switching is active. If the
addressed processor is not ready for further transmis-
sions on the I
2
C bus, the clock line SCL is pulled low.
This puts the current transmission into a wait state. After
a certain period of time, the VPX releases the clock and
the interrupted transmission is carried on.
FP
μ
controller
0
ff
Read Address
Write Address
Data
Status
0
ff
I
2
C
subaddress
space
FP
subaddress
space
Fig. 4–2:
FP register addressing
Write to FP
S
1 0 0 0 0 1 1 0
ACK
FPWR
ACK
send FP-address-
byte high
ACK
send FP-address-
byte low
ACK
P
S
1 0 0 0 0 1 1 0
ACK
FPDAT
ACK
send data-byte
high
ACK
send data-byte
low
ACK
P
Read from FP
S
1 0 0 0 0 1 1 0
ACK
FPRD
ACK
send FP-address-
byte high
ACK
send FP-address-
byte low
ACK
P
S
1 0 0 0 0 1 1 0
ACK
FPDAT
ACK
S
1 0 0 0 0 1 1 1
ACK
receive data-byte
high
ACK
receive data-byte
low
NAK
P