- 您現在的位置：買賣IC網 > PDF目錄359412 > VPX3224E (MICRONAS SEMICONDUCTOR HOLDING AG) Video Pixel Decoders PDF資料下載
參數資料
| 型號： | VPX3224E |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數： | 21/92頁 |
| 文件大小： | 616K |
| 代理商： | VPX3224E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
ADVANCE INFORMATION
VPX 322xE
MICRONAS INTERMETALL
21
2.7.1.3. Embedded Timing Codes (BStream)
In this mode, several event words are inserted into the
pixel stream for timing information. It is activated by set-
ting Bit[1:0] of FP-RAM 0x150 to 10. Each event word
consists of a chrominance code value containing the
phase of the color-multiplex followed by a luminance
code value signalling a specific event. The allowed con-
trol codes are listed in Table 2–5 and 2–6.
At the beginning and the end of each active video line,
timing reference codes (start of active video: SAV; end
of active video: EAV) are inserted with the beginning and
the end of VACT (see Fig. 2–23). Since VACT is sup-
pressed during blanked lines, video data and SAV/EAV
codes are present during active lines only. If raw/sliced
data should be output, VACT has to be enabled during
the VBI window with bit[2] of FP-RAM 0x138! In the case
of several windows per field, the length of the active data
stream per line can vary. Since the qualifiers for active
video (SAV/EAV) are independent of the other reference
codes, there is no influence on horizontal or vertical
syncs, and sync generation can be performed even with
several different windows. For full compliance with ap-
plications requiring data streams of a constant size, the
VPX provides a mode with programmable ‘video active’
signal VACT which can be selected via bit[2] of FP-RAM
0x140. The start and end positions of VACT relative to
HREF is determined by FP-RAM 0x151 and 0x152. The
delay of valid data relative to the leading edge of HREF
is calculated with the formulas given in Table 2–7 and
2–8. The result can be read in FP-RAM 0x10f (for win-
dow 1) and 0x11f (for window 2). Be aware that the larg-
est window defines the size of the needed memory. In
the case of 1140 raw VBI-samples and only 32 scaled
video samples, the graphics controller needs 570 words
for each line (the VBI-samples are multiplexed to lumi-
nance and chrominance paths).
The leading edge of HREF indicates the beginning of a
new video line. Depending on the type of the current line
(active or blanked), the corresponding horizontal refer-
ence code is inserted. For big window sizes, the leading
edge of HREF can arrive before the end of the active
data. In this case, hardware assures that the control
code for HREF is delayed and inserted after EAV only.
The VREF control code is inserted at the falling edge of
VREF. The state of HREF at this moment indicates the
current field type (HREF = 0: odd field; HREF = 1: even
field).
In this mode, the words 0, 1, 254, and 255 are reserved
for data identifications. This is assured by limitation of
the video data.
2.7.2. Bus Shuffler
In the YC
b
C
r
4:2:2 mode, the output of luminance data
is on port A and chrominance data on port B. With the
bus shuffler, luminance can be switched to port B and
chrominance to port A. In 8-bit double clock mode, shuf-
fling can be used to swap the Y and C components. It is
selected with FP-RAM 0x150.
Table 2–5:
Chrominance control codes
Chroma Value
Phase Information
FE
C
r
pixel
FF
C
b
pixel
2.7.3. Output Multiplexer
During normal operation, a 16-bit YC
b
C
r
4:2:2 data
stream is transferred synchronous to an internally gen-
erated PIXCLK at a rate of 13.5 MHz. Data can be
latched onto the falling edge of PIXCLK or onto the rising
edge of LLC during high PIXCLK. In the double clock
mode, luminance and chrominance data are multi-
plexed to 8 bit and transferred at the double clock fre-
quency of 27 MHz in the order C
b
, Y, C
r
, Y...; the first valid
chrominance value being a C
b
sample. With shuffling
switched on, Y and C components are swapped. Data
can be latched with the rising edge of LLC or alternating
edges of PIXCLK. This mode is selected with bit[9] of
FP-RAM 0x154. All 8-bit modes use Port A only. In this
case, Port B can be used as input or activated as pro-
grammable output with bit[8] of FP-RAM 0x154. Bit[0–7]
determine the state of Port B (see Fig. 2–22).
7:0
8
video data
=0
=1
B[7:0]
FP-RAM 0x154 [outmux]
Fig. 2–22:
Port B as input or programmable output port
8
8
Port
ben
7:0
from
controller
to
controller
I2C 0xAB
8
2.7.4. Output Ports
The two 8-bit ports produce TTL level signals coded in
binary offset. The Ports can be tristated either via the
output enable pin (OE) or via I
2
C register 0xF2. For more
information, see section 2.18. “Enable/Disable of Output
Signals”.
相關PDF資料 |
PDF描述 |
|---|---|
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
| VQ1001J | Dual N-Channel 30-V (D-S) MOSFET with Schottky Diode |
| VQ1001J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓30V，夾斷電流0.83A的N溝道增強型MOSFET) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| VPX3225D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3225D-C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| VPX3225E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
| VPX3226E | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
| VPX322XE | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Pixel Decoders |
發(fā)布緊急采購，3分鐘左右您將得到回復。