
ADVANCE INFORMATION
VPX 322xE
MICRONAS INTERMETALL
76
FP-RAM VPX Front-End
Name
Default
Function
Mode
Number
of Bits
Address
Hex
h’21
12
w/r
Input select:
Writing to this register will also initialize the standard.
bit[1:0]
luma selector
00
01
10
11
chroma selector
0/1
IF compensation
00
01
10
11
chroma bandwidth selector
00
narrow
01
normal
10
broad
11
wide
0/1
adaptive/fixed SECAM notch filter
0/1
enable luma lowpass filter
hpll speed
00
no change
01
terrestrial
10
vcr
11
mixed
status bit, write 0; This bit is set to 1 to indicate
operation complete.
VIN3
VIN2
VIN1
reserved
bit[2]
VIN1/CIN
bit[4:3]
off
6 dB/Okt
12 dB/Okt
10 dB/MHz only for SECAM
bit[6:5]
bit[7]
bit[8]
bit[10:9]
bit[11]
00
1
00
10
0
0
3
insel
vis
cis
ifc
cbw
fntch
lowp
hpllmd
h’22
12
w/r
picture start position, This register sets the start point of active vid-
eo. This can be used e.g. for panning. The setting is updated when
’sdt’ register is updated
0
sfif
h’23
12
w/r
luma/chroma delay adjust, The setting is updated when ’sdt’ register
is updated
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks, allowed range is +1 ... –7
0
ldly
Comb Filter
h’28
12
w/r
comb filter control register
bit[1:0]
notch filter select
00
01
10
11
flat frequency characteristic
min. peaked
med. peaked
max. peaked
bit[3:2]
diagonal dot reduction
00
11
horizontal difference gain
00
11
vertical difference gain
00
11
bit[11:8] vertical peaking gain
0
15
min. reduction
max. reduction
bit[4:5]
min. gain
max. gain
bit[7:6]
max. gain
min. gain
no vertical peaking
max. vertical peaking
h’e7
3
1
2
3
0
comb_uc
nosel
ddr
hdg
vdg
vpk
h’55
12
w/r
comb filter test register
bit[1:0]
bit[2]
reserved, set ot 0
0/1
disable/enable vertical peaking
DC rejection filter
disable/enable vertical peaking
coring
bit[3]
0/1
bit[11:4] reserved, set to 0
0
misc_cmb_tst
dcr
cor